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altera corporation section i?1 preliminary section i. cyclone fpga family data sheet this section provides designers with the data sheet specifications for cyclone ? devices. the chapters contain fe ature definitions of the internal architecture, configuration and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power consumption, and ordering info rmation for cyclone devices. this section contains the following chapters: chapter 1. introduction chapter 2. cyclone architecture chapter 3. configuration & testing chapter 4. dc & switching characteristics chapter 5. reference & ordering information revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section i?2 altera corporation preliminary revision history cyclone device handbook, volume 1
altera corporation 1?1 january 2007 preliminary 1. introduction introduction the cyclone ? field programmable gate array family is based on a 1.5-v, 0.13- m, all-layer copper sram process, with densities up to 20,060 logic elements (les) and up to 288 kbits of ram. with features like phase- locked loops (plls) for clocking and a dedicated double data rate (ddr) interface to meet ddr sdram and fast cycle ram (fcram) memory requirements, cyclone devices are a co st-effective solution for data-path applications. cyclone devices support various i/o standards, including lvds at data rates up to 640 megabits per second (mbps), and 66- and 33-mhz, 64- and 32-bit peripheral co mponent interconnect (pci), for interfacing with and supporting assp and asic devices. altera also offers new low-cost serial configuration devices to configure cyclone devices. the following shows the main sections in the cyclone fpga family data sheet: section page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 logic array blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 logic elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 multitrack interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?12 embedded memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?18 global clock network & phase-locked loops. . . . . . . . . . . 2?29 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?39 power sequencing & hot socketing . . . . . . . . . . . . . . . . . . . . 2?55 ieee std. 1149.1 (jtag) boundary scan support . . . . . . . . . . 3?1 signaltap ii embedded logic analyzer . . . . . . . . . . . . . . . . . 3?5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9 software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 device pin-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 c51001-1.4
1?2 altera corporation preliminary january 2007 cyclone device handbook, volume 1 features the cyclone device family offers the following features: 2,910 to 20,060 les, see table 1?1 up to 294,912 ram bits (36,864 bytes) supports configuration through low-cost serial configuration device support for lvttl, lvcmos, sstl-2, and sstl-3 i/o standards support for 66- and 33-mhz, 64- and 32-bit pci standard high-speed (640 mbps) lvds i/o support low-speed (311 mbps) lvds i/o support 311-mbps rsds i/o support up to two plls per device provid e clock multiplication and phase shifting up to eight global clock lines with six clock resources available per logic array block (lab) row support for external memory, including ddr sdram (133 mhz), fcram, and single data rate (sdr) sdram support for multiple intellectual property (ip) cores, including altera ? megacore ? functions and altera megafunctions partners program (ampp sm ) megafunctions. table 1?1. cyclone device features feature ep1c3 ep1c4 ep1c6 ep1c12 ep1c20 les 2,910 4,000 5,980 12,060 20,060 m4k ram blocks (128 36bits)1317205264 total ram bits 59,904 78,336 92,160 239,616 294,912 plls 12222 maximum user i/o pins (1) 104 301 185 249 301 note to ta b l e 1 ? 1 : (1) this parameter includes global clock pins.
altera corporation 1?3 january 2007 preliminary features cyclone devices are availa ble in quad flat pack (qfp) and space-saving fineline ? bga packages (see table 1?2 through 1?3 ). vertical migration means you can mi grate a design from one device to another that has the same dedicated pins, jtag pins, and power pins, and are subsets or supersets for a given pa ckage across device densities. the largest density in any package has the highest number of power pins; you must use the layout for the larges t planned density in a package to provide the necessary po wer pins for migration. for i/o pin migration across densitie s, cross-reference the available i/o pins using the device pin-outs for all planned densities of a given package type to identify which i/o pins can be migrated. the quartus ? ii software can automatically cross-reference and place all pins for you when given a device migration list. if one device has power or ground pins, but these same pins are user i/o on a different device that is in the migration path,the quartus ii software ensures the pins are not used as user i/o in the quartus ii software. en sure that these pins are connected to the appropriate plane on the board. the quartus ii software reserves i/o pins as power pins as necessary for layout with the larger densities in the same package having more power pins. table 1?2. cyclone package options & i/o pin counts device 100-pin tqfp (1) 144-pin tqfp (1) , (2) 240-pin pqfp (1) 256-pin fineline bga 324-pin fineline bga 400-pin fineline bga ep1c3 65 104 ep1c4 249 301 ep1c6 98 185 185 ep1c12 173 185 249 ep1c20 233 301 notes to ta b l e 1 ? 2 : (1) tqfp: thin quad flat pack. pqfp: plastic quad flat pack. (2) cyclone devices support vertical migration within the same package (i.e., designers can migrate between the ep1c3 device in the 144-pin tqfp package and the ep1c6 device in the same package)
1?4 altera corporation preliminary january 2007 cyclone device handbook, volume 1 document revision history table 1?4 shows the revision history for this document. table 1?3. cyclone qfp & fineline bga package sizes dimension 100-pin tqfp 144-pin tqfp 240-pin pqfp 256-pin fineline bga 324-pin fineline bga 400-pin fineline bga pitch (mm) 0.5 0.5 0.5 1.0 1.0 1.0 area (mm 2 ) 256 484 1,024 289 361 441 length width (mm mm) 16 16 22 22 34.6 34.6 17 17 19 19 21 21 table 1?4. document revision history date & document version changes made summary of changes january 2007 v1.4 added document revision history. august 2005 v1.3 minor updates. october 2003 v1.2 added 64-bit pci support information. september 2003 v1.1 updated lvds data rates to 640 mbps from 311 mbps. updated rsds feature information. may 2003 v1.0 added document to cyclone device handbook.
altera corporation 2?1 january 2007 preliminary 2. cyclone architecture functional description cyclone ? devices contain a two-dimensional row- and column-based architecture to implement custom lo gic. column and row interconnects of varying speeds provide signal interconnects between labs and embedded memory blocks. the logic array consists of labs, with 10 les in each lab. an le is a small unit of logic providing effici ent implementation of user logic functions. labs are grouped into ro ws and columns across the device. cyclone devices range between 2,910 to 20,060 les. m4k ram blocks are true dual-port memory blocks with 4k bits of memory plus parity (4, 608 bits). these blocks provide dedicated true dual-port, simple dual-port, or sing le-port memory up to 36-bits wide at up to 250 mhz. these blocks are grouped into columns across the device in between certain labs. cyclone devices offer between 60 to 288 kbits of embedded ram. each cyclone device i/o pin is fed by an i/o element (ioe) located at the ends of lab rows and columns around the periphery of the device. i/o pins support various single-ended and differential i/o standards, such as the 66- and 33-mhz, 64- and 32-bit pci standard and the lvds i/o standard at up to 640 mbps. each ioe contains a bidirectional i/o buffer and three registers for registering input, output, and output-enable signals. dual-purpose dq s, dq, and dm pins along with delay chains (used to phase-align ddr signals) provide interface support with external memory devices such as ddr sdram, and fcram devices at up to 133 mhz (266 mbps). cyclone devices provide a global cl ock network and up to two plls. the global clock network consists of ei ght global clock lines that drive throughout the entire device. the global clock network can provide clocks for all resources within the device, such as ioes, les, and memory blocks. the global clock lines can also be used for control signals. cyclone plls provide general-purpose clocki ng with clock multiplication and phase shifting as well as external outputs for high -speed differential i/o support. figure 2?1 shows a diagram of the cyclone ep1c12 device. c51002-1.5
2?2 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?1. cyclone ep1c12 device block diagram the number of m4k ram blocks, pl ls, rows, and columns vary per device. table 2?1 lists the resources available in each cyclone device. logic array pll ioes m4k blocks ep1c12 device table 2?1. cyclone device resources device m4k ram plls lab columns lab rows columns blocks ep1c3 1 13 1 24 13 ep1c4 1 17 2 26 17 ep1c6 1 20 2 32 20 ep1c12 2 52 2 48 26 ep1c20 2 64 2 64 32
altera corporation 2?3 january 2007 preliminary logic array blocks logic array blocks each lab consists of 10 les, le carry chains, lab control signals, a local interconnect, look-up table (lut) chai n, and register chain connection lines. the local interconnect transf ers signals between les in the same lab. lut chain connections transfer the output of one le's lut to the adjacent le for fast sequential lu t connections within the same lab. register chain connections transfer th e output of one le's register to the adjacent le's register wi thin an lab. the quartus ? ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, lut chain, and register chain connections for performance and area efficiency. figure 2?2 details the cyclone lab. figure 2?2. cyclone lab structure lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. neighboring labs, plls, and m4k ram blocks from the left and right can also drive an lab's local interconnect through the direct link connection. the direct link connection feature minimizes the use of row and column interconnects, providing higher direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnect column interconnect local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block
2?4 altera corporation preliminary january 2007 cyclone device handbook, volume 1 performance and flexibility. each le can drive 30 other les through fast local and direct link interconnects. figure 2?3 shows the direct link connection. figure 2?3. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include two clocks, two clock enables, two asynchronous clears, synchronous cl ear, asynchronous preset/load, synchronous load, and add/subtract control signals. this gives a maximum of 10 control signals at a ti me. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. each lab can use two clocks and two clock enable signals. each lab's clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal will also use labclkena1 . if the lab uses both the rising and falling edges of a clock, it also uses both lab-wide clock signals. de-asserting th e clock enable signal will turn off the lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous load/preset signal. the as ynchronous load acts as a preset when the asynchronous load data input is tied high. lab direct link interconnect to right direct link interconnect from right lab, m4k memory block, pll, or ioe output direct link interconnect from left lab, m4k memory block, pll, or ioe output local interconnect direct link interconnect to left
altera corporation 2?5 january 2007 preliminary logic elements with the lab-wide addnsub control signal, a single le can implement a one-bit adder and subtractor. this saves le resources and improves performance for logic functions such as dsp correlators and signed multipliers that alternate between addition and subtraction depending on data. the lab row clocks [5..0] and lab local interconnect generate the lab- wide control signals. the multitrack tm interconnect's inherent low skew allows clock and control signal di stribution in addition to data. figure 2?4 shows the lab control signal generation circuit. figure 2?4. lab-wide control signals logic elements the smallest unit of logic in the cy clone architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le contains a four-input lut, which is a function generator that can implement any function of four variable s. in addition, each le contains a programmable register and carry chain with carry select capability. a single le also supports dynamic single bit addition or subtraction mode selectable by an lab-wide control signal. each le drives all types of interconnects: local, row, column, lut chain, register chain, and direct link interconnects. see figure 2?5 . labclkena1 labclk2 labclk1 labclkena2 asyncload or labpre syncload dedicated lab row clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclr1 labclr2 synclr addnsub 6
2?6 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?5. cyclone le each le's programmable register can be configured for d, t, jk, or sr operation. each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. global signals, general-purpose i/o pins, or any internal logic can drive the register's clock and clear control signals. ei ther general-purpose i/o pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. the asynchronous load data input comes from the data3 input of the le. for combinator ial functions, the lut output bypasses the register and drives directly to the le outputs. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources. this allows the lut to drive one output while the register drives another output. this feature, called register packing, improves device utilization because the device can use the register and the lut for unrelated labclk1 labclk2 labclr2 labpre/aload carry-in1 carry-in0 lab carry-in clock & clock enable select lab carry-out carry-out1 carry-out0 look-up ta b l e (lut) carry chain row, column, and direct link routing row, column, and direct link routing programmable register prn/ald clrn d q ena register bypass packed register select chip-wide reset labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load logic data1 data2 data3 data4 lut chain routing to next le labclr1 local routing register chain output a data addnsub register feedback register chain routing from previous le
altera corporation 2?7 january 2007 preliminary logic elements functions. another special packing mo de allows the register output to feed back into the lut of the same le so that the register is packed with its own fan-out lut. this provides another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. lut chain & register chain in addition to the three general routing outputs, the les within an lab have lut chain and register chain ou tputs. lut chain connections allow luts within the same lab to cascad e together for wide input functions. register chain outputs allow register s within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinatorial function and the register s to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local interconnect resources. ?multitrack interconnect? on page 2?12 for more information on lut chain and register chain connections. addnsub signal the le's dynamic adder/subtractor feature saves logic resources by using one set of les to implement both an adder and a subtractor. this feature is controlled by the lab-wide control signal addnsub . the addnsub signal sets the lab to perform either a + b or a ? b. the lut computes addition; subtraction is computed by adding the two's complement of the intended subtractor . the lab-wide signal converts to two's complement by inverting the b bits within the lab and setting carry-in = 1 to add one to the least si gnificant bit (lsb). the lsb of an adder/subtractor must be placed in the first le of the lab, where the lab-wide addnsub signal automatic ally sets the carry-in to 1. the quartus ii compiler automatically plac es and uses the adder/subtractor feature when using adder/subtra ctor parameterized functions. le operating modes the cyclone le can operate in one of the following modes: normal mode dynamic arithmetic mode each mode uses le resources differently. in each mode, eight available inputs to the le ? the four data inputs from the lab local interconnect, carry-in0 and carry-in1 from the previous le, the lab carry-in from the previous carry-chain lab, and the register chain connection ? are directed to different destinations to implement the desire d logic function. lab-wide signals provide clock, asynchronous clear, asynchronous
2?8 altera corporation preliminary january 2007 cyclone device handbook, volume 1 preset/load, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes. the addnsub control signal is allowed in arithmetic mode. the quartus ii software, in conjunct ion with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinatorial functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?6 ). the quartus ii compiler automaticall y selects the carry-in or the data3 signal as one of the inputs to th e lut. each le can use lut chain connections to drive its combinatorial ou tput directly to the next le in the lab. asynchronous load data fo r the register comes from the data3 input of the le. les in normal mode support packed registers. figure 2?6. le in normal mode note to figure 2?6 : (1) this signal is only allowed in normal mode if the le is at the end of an adder/subtractor chain. data1 4-input lut data2 data3 cin (from cout of previous le) data4 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) aload (lab wide) ald/pre clrn d q ena a data sclear (lab wide) sload (lab wide) register chain connection lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback (1)
altera corporation 2?9 january 2007 preliminary logic elements dynamic arithmetic mode the dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. an le in dynamic arithmetic mode uses four 2-input luts configurable as a dynamic adder/subtractor. the first two 2-input luts compute two summations based on a possible carry-in of 1 or 0; the other two luts generate carry outputs for the two chains of the ca rry select circuitry. as shown in figure 2?7 , the lab carry-in signal selects either the carry-in0 or carry-in1 chain. the selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. for example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 the other two luts use the data1 and data2 signals to generate two possible carry-out signals ? one for a carry of 1 and the other for a carry of 0. the carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the dynamic arithmetic mode also of fers clock enable, counter enable, synchronous up/down control, sync hronous clear, sy nchronous load, and dynamic adder/subtrac tor options. the lab local interconnect data inputs generate the counter enable and synchronous up/down control signals. the synchronous clear and synchronous load options are lab- wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. the addnsub lab-wide signal controls whether the le acts as an adder or subtractor.
2?10 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?7. le in dynamic arithmetic mode note to figure 2?7 : (1) the addnsub signal is tied to the carry input for the first le of a carry chain only. carry-select chain the carry-select chain provides a very fast carry-select function between les in dynamic arithmetic mode. the carry-select chain uses the redundant carry calculation to increase the speed of carry functions. the le is configured to calculate outputs for a possible carry-in of 0 and carry- in of 1 in parallel. the carry-in0 and carry-in1 signals from a lower- order bit feed forward into the higher-o rder bit via the parallel carry chain and feed into both the lut and the next portion of the carry chain. carry- select chains can begin in any le within an lab. the speed advantage of the carry-select chain is in the parallel pre- computation of carry chains. si nce the lab carry-in selects the precomputed carry ch ain, not every le is in th e critical path. only the propagation delays between lab carry-in generation (le 5 and le 10) are now part of the critical path. this fe ature allows the cyclone architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. data1 lut data2 data3 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) ald/pre clrn d q ena a data re g ister chain connection lut lut lut carry-out1 carry-out0 lab carry-in carry-in0 carry-in1 (1) sclear (lab wide) sload (lab wide) lut chain connection re g ister chain output row, column, and direct link routin g row, column, and direct link routin g local routin g aload (lab wide) reg i ster f eedbac k
altera corporation 2?11 january 2007 preliminary logic elements figure 2?8 shows the carry-select circuitry in an lab for a 10-bit full adder. one portion of the lut generates the sum of two bits using the input signals and the appr opriate carry-in bit; the sum is routed to the output of the le. the register can be bypassed for simple adders or used for accumulator functions. another portion of the lut generates carry- out bits. an lab-wide carry-in bit selects which chain is used for the addition of given inputs. the ca rry-in signal for each chain, carry-in0 or carry-in1 , selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. th e final carry-out signal is routed to an le, where it is fed to local, row, or column interconnects. figure 2?8. carry select chain le4 le3 le2 le1 a1 b1 a2 b2 a3 b3 a4 b4 sum1 sum2 sum3 sum4 le10 le9 le8 le7 a7 b7 a8 b8 a9 b9 a10 b10 sum7 le6 a6 b6 sum6 le5 a5 b5 sum5 sum8 sum9 sum10 01 01 lab carry-in lab carry-out lut lut lut lut data1 lab carry-in data2 carry-in0 carry-in1 carry-out0 carry-out1 sum
2?12 altera corporation preliminary january 2007 cyclone device handbook, volume 1 the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carr y chains longer than 10 les by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically allowing fa st horizontal co nnections to m4k memory blocks. a carry chain can co ntinue as far as a full column. clear & preset logic control lab-wide signals control the logic for the register's clear and preset signals. the le directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynchro nous preset does not require a not- gate push-back technique. cyclone devices support simultaneous preset/ asynchronous load and clear signals. an asynchronous clear signal takes precedence if both signals are as serted simultaneously. each lab supports up to two clears and one preset signal. in addition to the clear and preset po rts, cyclone devices provide a chip- wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the qu artus ii software controls this pin. this chip-wide reset overrides all other control signals. multitrack interconnect in the cyclone architecture, conn ections between les, m4k memory blocks, and device i/o pins are provided by the multitrack interconnect structure with directdrive tm technology. the multitrack interconnect consists of continuous, performance- optimized routing lines of different speeds used for inter- and intra-desi gn block connectivity. the quartus ii compiler automatically places cr itical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when
altera corporation 2?13 january 2007 preliminary multitrack interconnect migrating through different device densities. dedicated row interconnects route signals to and from labs, plls, and m4k memory blocks within the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing fo ur blocks to the right or left the direct link interconnect allo ws an lab or m4k memory block to drive into the local interconnect of it s left and right neighbors. only one side of a pll block interfaces with di rect link and row interconnects. the direct link interconnect provides fast communication between adjacent labs and/or blocks without us ing row interconnect resources. the r4 interconnects span four labs, or two labs and one m4k ram block. these resources are used for fast row connections in a four-lab region. every lab has its own set of r4 interconnects to drive either left or right. figure 2?9 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by m4k memory blocks, plls, and row ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects that drive to the right, the primary lab and right neighbor can dr ive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 inte rconnects for connections from one row to another.
2?14 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?9. r4 interconnect connections notes to figure 2?9 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. the column interconnect operates similarly to the row interconnect. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, m4k memory blocks, and row and column ioes. these column resources include: lut chain interconne cts within an lab register chain intercon nects within an lab c4 interconnects traversing a distan ce of four blocks in an up and down direction cyclone devices include an enhanced interconnect struct ure within labs for routing le output to le input connections faster using lut chain connections and register chain conne ctions. the lut chain connection allows the combinatorial output of an le to directly drive the fast input of the le right below it, bypassing the local interconnect. these resources can be used as a high-spe ed connection for wide fan-in functions from le 1 to le 10 in the same lab. the register chain connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. the quartus ii compiler automatically takes advantage of th ese resources to improve utilization and performance. figure 2?10 shows the lut chain and register chain interconnects. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
altera corporation 2?15 january 2007 preliminary multitrack interconnect figure 2?10. lut chain & register chain interconnects the c4 interconnects span four labs or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?11 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture blocks, incl uding plls, m4k memory blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 lut chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab
2?16 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?11. c4 inte rconnect connections note (1) note to figure 2?11 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect
altera corporation 2?17 january 2007 preliminary multitrack interconnect all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (i.e., m4k memory or pll) connects to row and column interconnects and has loca l interconnect regions driven by row and column interconnects. thes e blocks also have direct link interconnects for fast connections to and from a neighboring lab. table 2?2 shows the cyclone device's routing scheme. table 2?2. cyclone device routing scheme source destination lut chain register chain local interconnect direct link interconnect r4 interconnect c4 interconnect le m4k ram block pll column ioe row ioe lut chain v register chain v local interconnect vvvvv direct link interconnect v r4 interconnect vvv c4 interconnect vvv le vvvvvv m4k ram block vvvv pll vvv column ioe v row ioe vvv
2?18 altera corporation preliminary january 2007 cyclone device handbook, volume 1 embedded memory the cyclone embedded memory cons ists of columns of m4k memory blocks. ep1c3 and ep1c6 devices have one column of m4k blocks, while ep1c12 and ep1c20 devices have two columns (see table 1?1 on page 1?2 for total ram bits per density). each m4k block can implement various types of memory wi th or without parity, in cluding true dual-port, simple dual-port, and single-port ram, rom, and fifo buffers. the m4k blocks support th e following features: 4,608 ram bits 250 mhz performance true dual-port memory simple dual-port memory single-port memory byte enable parity bits shift register fifo buffer rom mixed clock mode 1 violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. memory modes the m4k memory blocks in clude input registers that synchronize writes and output registers to pipeline designs and improve system performance. m4k blocks offer a tr ue dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 2?12 shows true dual-port memory. figure 2?12. true dual-port memory configuration data a [ ] address a [ ] wren a clock a clocken a q a [ ] aclr a data b [ ] address b [ ] wren b clock b clocken b q b [ ] aclr b ab
altera corporation 2?19 january 2007 preliminary embedded memory in addition to true dual-port memory, the m4k memory blocks support simple dual-port and single-port ram. simple dual-port memory supports a simultaneous read and write. single-port memory supports non-simultaneous reads and writes. figure 2?13 shows these different m4k ram memory port configurations. figure 2?13. simple dual-port & singl e-port memory configurations note to figure 2?13 : (1) two single-port memory blocks can be implemented in a single m4k block as long as each of the two independent block sizes is equal to or less than half of the m4k block size. the memory blocks also enable mixed-width data ports for reading and writing to the ram ports in dual-por t ram configuration. for example, the memory block can be written in 1 mode at port a and read out in 16 mode from port b. the cyclone memory architecture can implement fully synchronous ram by registering both the input and output signals to the m4k ram block. all m4k memory block in puts are registered, providing synchronous write cycles. in synchr onous operation, the memory block generates its own self-timed strobe write enable ( wren ) signal derived from a global clock. in contrast, a circuit using asynchronous ram must generate the ram wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr single-port memory (1) simple dual-port memory
2?20 altera corporation preliminary january 2007 cyclone device handbook, volume 1 signal. the output registers can be bypassed. pseudo-asynchronous reading is possible in the simple dual-port mode of m4k blocks by clocking the read enable and read ad dress registers on the negative clock edge and bypassing the output registers. when configured as ram or rom, you can use an initialization file to pre-load the memory contents. two single-port memory blocks can be implemented in a single m4k block as long as each of the two indepe ndent block sizes is equal to or less than half of the m4k block size. the quartus ii software automatically implements larger memory by combining multiple m4k memory blocks. for example, two 256 16-bit ram blocks can be combined to form a 256 32-bit ram block. memory performance does not degrade for memory blocks using the maximum number of words allowed. logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. to create a larger high-speed memory block, the qu artus ii software automatically combines memory blocks with le control logic. parity bit support the m4k blocks support a parity bit fo r each byte. the parity bit, along with internal le logic, can implemen t parity checking for error detection to ensure data integrity. you can also use parity-size data words to store user-specified control bits. byte enab les are also available for data input masking during write operations. shift register support you can configure m4k memory blocks to implement shift registers for dsp applications such as pseudo-random number generators, multi- channel filtering, auto-correlation, and cross-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for la rge shift registers. a more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with th e dedicated circuitry. the size of a w m n shift register is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). the size of a w m n shift register must be less than or equal to the maximum number of memory bits in the m4k block (4, 608 bits). the total number of shift
altera corporation 2?21 january 2007 preliminary embedded memory register outputs (number of taps n width w ) must be less than the maximum data width of the m4k ram block ( 36). to create larger shift registers, multiple memory bl ocks are cascaded together. data is written into each address locati on at the falling edge of the clock and read from the address at the rising edge of the clock. the shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 2?14 shows the m4k memory block in the shift register mode. figure 2?14. shift register memory configuration memory configuration sizes the memory address depths and outp ut widths can be configured as 4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256 18 bits), and 128 32 (or 128 36 bits). the 128 32- or 36-bit configuration m -bit shift re g ister w w m -bit shift re g ister m -bit shift re g ister m -bit shift re g ister w w w w w w w m n shift re g ister n nu mbe r o f t aps
2?22 altera corporation preliminary january 2007 cyclone device handbook, volume 1 is not available in the true dual-p ort mode. mixed-width configurations are also possible, allowing dif ferent read and write widths. tables 2?3 and 2?4 summarize the possible m4k ram block configurations. when the m4k ram block is configured as a shift register block, you can create a shift register up to 4,608 bits ( w m n ). table 2?3. m4k ram block confi gurations (simple dual-port) read port write port 4k 12k 21k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvv v v v 2k 2 vvv v v v 1k 4 vvv v v v 512 8 vvv v v v 256 16 vvv v v v 128 32 vvv v v v 512 9 vv v 256 18 vv v 128 36 vv v table 2?4. m4k ram block confi gurations (true dual-port) port a port b 4k 12k 21k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv
altera corporation 2?23 january 2007 preliminary embedded memory byte enables m4k blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. the byte enable s allow the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. table 2?5 summarizes the byte selection. control signals & m4k interface the m4k blocks allow for different cl ocks on their inpu ts and outputs. either of the two clocks feeding th e block can clock m4k block registers ( renwe , address, byte enable, datain , and output registers). only the output register can be bypassed. the six labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?15 . the r4, c4, and direct link interconnects from adjacent labs drive the m4k block local interconnect. the m4k blocks can communicate with labs on either the left or right side through these row resources or with lab columns on either the right or left with the column resources. up to 10 direct link input connections to the m4k block are possible from the left adjacent labs and another 10 poss ible from the right adjacent lab. m4k block outputs can also connect to left and right labs through 10 direct link interconnects each. figure 2?16 shows the m4k block to logic array interface. table 2?5. byte enable for m4k blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 ? [26..18] [3] = 1 ? [35..27] notes to ta b l e 2 ? 5 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16 and 32 modes.
2?24 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?15. m4k ram bl ock control signals figure 2?16. m4k ram block lab row interface clocken_a renwe_a clock_a alcr_a alcr_b renwe_b dedicated lab row clocks local interconnect local interconnect local interconnect local interconnect local interconnect clocken_b clock_b 6 local interconnect local interconnect local interconnect local interconnect local interconnect dataout m4k ram block datain address 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnects r4 interconnects lab row clocks clocks byte enable control signals 6
altera corporation 2?25 january 2007 preliminary embedded memory independent clock mode the m4k memory blocks implement independent clock mode for true dual-port memory. in this mode, a separate clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port, a and b, also supports independent clock enables and asynchronous clear signals for port a and b registers. figure 2?17 shows an m4k memory block in independent clock mode. figure 2?17. independent clock mode notes (1) , (2) notes to figure 2?17 : (1) all registers shown have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. input/output clock mode input/output clock mode can be im plemented for both the true and simple dual-port memory modes. on ea ch of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock co ntrols the block's data output registers. each memory block port, a or b, also supports independent clock enables and asynchronous cl ear signals for input and output registers. figures 2?18 and 2?19 show the memory block in input/output clock mode. 6 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read ena b le data o u t data in address b write/read ena b le data o u t clken a clock a d ena q w ren a 6 lab ro w clocks q a [ ] 6 data b [ ] address b [ ] clken b clock b w ren b q b [ ] ena ab ena d q d ena q b yteena a [ ] byte ena b le a byte ena b le b b yteena b [ ] ena d q ena d q ena d q d q write p u lse generator write p u lse generator
2?26 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?18. input/output clock mode in true dual-port mode note (1) , (2) notes to figure 2?18 : (1) all registers shown have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 6 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read ena b le data o u t data in address b write/read ena b le data o u t clken a clock a d ena q w ren a 6 lab ro w clocks q a [ ] 6 data b [ ] address b [ ] clken b clock b w ren b q b [ ] ena ab ena d q ena d q ena d q d q d ena q b yteena a [ ] byte ena b le a byte ena b le b b yteena b [ ] ena d q write p u lse generator write p u lse generator
altera corporation 2?27 january 2007 preliminary embedded memory figure 2?19. input/output clock mode in simple dual-port mode notes (1) , (2) notes to figure 2?19 : (1) all registers shown except the rden register have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q w raddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in read address write address write ena b le read ena b le data o u t o u tclken inclken inclock o u tclock w ren rden 6 lab ro w clocks to m u ltitrac k interconnect d ena q b yteena[ ] byte ena b le write p u lse generator
2?28 altera corporation preliminary january 2007 cyclone device handbook, volume 1 read/write clock mode the m4k memory blocks implement re ad/write clock mode for simple dual-port memory. you can use up to two clocks in this mode. the write clock controls the block's data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . the memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. figure 2?20 shows a memory block in read/write clock mode. figure 2?20. read/write clock m ode in simple dual-port mode notes (1) , (2) notes to figure 2?20 : (1) all registers shown except the rden register have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q w raddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in read address write address write ena b le read ena b le data o u t rdclken w rclken w rclock rdclock w ren rden 6 lab ro w clocks to m u ltitrac k interconnect d ena q b yteena[ ] byte ena b le write p u lse generator
altera corporation 2?29 january 2007 preliminary global clock network & phase-locked loops single-port mode the m4k memory blocks also suppo rt single-port mode, used when simultaneous reads and writes are not required. see figure 2?21 . a single m4k memory block can support up to two single-port mode ram blocks if each ram block is less than or equal to 2k bits in size. figure 2?21. single-port mode note (1) note to figure 2?21 : (1) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. global clock network & phase-locked loops cyclone devices provide a global cloc k network and up to two plls for a complete clock management solution. global clock network there are four dedicated clock pins ( clk[3..0] , two pins on the left side and two pins on the right side) that drive the global clock network, as shown in figure 2?22 . pll outputs, logic array, and dual-purpose clock ( dpclk[7..0] ) pins can also drive the global clock network. 6 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in address write ena b le data o u t o u tclken inclken inclock o u tclock write p u lse generator w ren 6 lab ro w clocks to m u ltitrac k interconnect
2?30 altera corporation preliminary january 2007 cyclone device handbook, volume 1 the eight global clock li nes in the global clock network drive throughout the entire device. the global clock network can provide clocks for all resources within the device ? ioes, les, and memory blocks. the global clock lines can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin, or dqs signals for ddr sdram or fcram inte rfaces. internal logic can also drive the global clock network for inte rnally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. figure 2?22 shows the various sources that drive the global clock network. figure 2?22. global clock generation note (1) notes to figure 2?22 : (1) the ep1c3 device in the 100-pin tqfp package has five dpclk pins ( dpclk2 , dpclk3 , dpclk4 , dpclk6 , and dpclk7 ). (2) ep1c3 devices only contain one pll (pll 1). (3) the ep1c3 device in the 100-pin tqfp package does not have dedicated clock pins clk1 and clk3 . 8 global clock network pll1 pll2 (2) clk0 clk1 (3) clk2 clk3 (3 ) dpclk1 dpclk0 dpclk4 dpclk5 dpclk2 dpclk3 dpclk7 dpclk6 2 2 from logic array from logic array 4 44 4 cyclone device
altera corporation 2?31 january 2007 preliminary global clock network & phase-locked loops dual-purpose clock pins each cyclone device except the ep 1c3 device has ei ght dual-purpose clock pins, dpclk[7..0] (two on each i/o bank). ep1c3 devices have five dpclk pins in the 100-pin tqfp pack age. these dual-purpose pins can connect to the global clock network (see figure 2?22 ) for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as trdy and irdy for pci, or dqs signals for external memory interfaces. combined resources each cyclone device contains eight distinct dedicated clocking resources. the device uses multiplexers with th ese clocks to form six-bit buses to drive lab row clocks, column ioe clocks, or row ioe clocks. see figure 2?23 . another multiplexer at the lab level selects two of the six lab row clocks to feed the le registers within the lab. figure 2?23. global clock network multiplexers ioe clocks have row and column bloc k regions. six of the eight global clock resources feed to these row and column regions. figure 2?24 shows the i/o clock regions. clock [7..0] column i/o region io_clk]5..0] lab row clock [5..0] row i/o region io_clk[5..0] global clocks [3..0] pll outputs [3..0] dual-purpose clocks [7..0] global clock network core logic [7..0]
2?32 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?24. i/o clock regions plls cyclone plls provide general- purpose clocking with clock multiplication and phase shifting as we ll as outputs for differential i/o support. cyclone devices contain two plls, except for the ep1c3 device, which contains one pll. column i/o clock region io_clk[5..0] column i/o clock region io_clk[5..0] 6 6 i/o clock region s i/o clock region s 8 global clock network row i/o region s cyclone logic array 6 6 lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] 6 6 6 6
altera corporation 2?33 january 2007 preliminary global clock network & phase-locked loops table 2?6 shows the pll features in cyclone devices. figure 2?25 shows a cyclone pll. figure 2?25. cyclone pll note (1) notes to figure 2?25 : (1) the ep1c3 device in the 100-pin tqfp package does not support external outputs or lvds inputs. the ep1c6 device in the 144-pin tqfp package does not support external output from pll2. (2) lvds input is supported via the secondary function of the dedicated clock pins. for pll 1, the clk0 pin?s secondary function is lvdsclk1p and the clk1 pin?s secondar y function is lvdsclk1n . for pll 2, the clk2 pin?s secondary function is lvdsclk2p and the clk3 pin?s secondary function is lvdsclk2n . (3) pfd: phase frequency detector. table 2?6. cyclone pll features feature pll support clock multiplication and division m /( n post-scale counter) (1) phase shift down to 125-ps increments (2) , (3) programmable duty cycle yes n umber of internal clock outputs 2 n umber of external clock outputs one differential or one single-ended (4) notes to ta b l e 2 ? 6 : (1) the m counter ranges from 2 to 32. the n counter and the post-scale counters range from 1 to 32. (2) the smallest phase shift is determined by the voltage- controlled oscillator (vco) period divided by 8. (3) for degree increments, cyclone device s can shift all output frequencies in increments of 45. smaller degree incr ements are possible depending on the frequency and divide parameters. (4) the ep1c3 device in the 100-pin tqfp package does not support external clock output. the ep1c6 device in the 144-pin tqfp package does not support external clock output from pll2. charge pump vco pfd (3) loop filter clk0 or lvdsclk1p (2) clk1 or lvdsclk1n (2) n m t t global cloc k global cloc k i/o buffer g0 g1 e vco phase selection selectable at each pll output port post-scale counters
2?34 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?26 shows the pll global clock connections. figure 2?26. cyclone pll gl obal clock connections notes to figure 2?26 : (1) pll 1 supports one single-end ed or lvds input via pins clk0 and clk1 . (2) pll2 supports one single-end ed or lvds input via pins clk2 and clk3 . (3) pll1_out and pll2_out support single-ended or lvds output. if external output is not required, these pins are available as regular user i/o pins. (4) the ep1c3 device in the 100-pin tqfp package does not support external clock output. the ep1c6 device in the 144-pin tqfp package does not suppor t external clock output from pll2. table 2?7 shows the global clock networ k sources available in cyclone devices. clk0 clk1 (1) pll1 pll2 g0 g1 e g0 g1 e pll1_out (3), (4) clk2 clk3 (2) pll2_out (3), (4 ) g0 g2 g1 g3 g4 g6 g5 g7 table 2?7. global clock network sources (part 1 of 2) source gclk0 gclk1 gclk2 gclk3 gclk4 gclk5 gclk6 gclk7 pll counter output pll1 g0 vv pll1 g1 vv pll2 g0 (1) vv pll2 g1 (1) vv dedicated clock input pins clk0 vv clk1 (2) vv clk2 vv clk3 (2) vv
altera corporation 2?35 january 2007 preliminary global clock network & phase-locked loops clock multiplication & division cyclone plls provide clock synthesis for pll output ports using m /( n post scale counter) scaling factors. the input clock is divided by a pre-scale divider, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter to divide down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least-common multiple of the output frequencies that meets its frequency specifications. then, the post-scale dividers scale down the output frequency for each output port. for example, if the output frequencies required from one pll are 33 and 66 mhz, the vco is set to 330 mhz (the least-common multiple in the vco's range). each pll has one pre-scale divider, n , that can range in value from 1 to 32. each pll also has one multiply divider, m , that can range in value from 2 to 32. global clock outputs ha ve two post scale g dividers for global clock outputs, and external clock outputs have an e divider for external clock output, b oth ranging from 1 to 32. the quartus ii software automatically chooses the appropriat e scaling factors according to the input frequency, multiplication, and division values entered. dual-purpose clock pins dpclk0 (3) v dpclk1 (3) v dpclk2 v dpclk3 v dpclk4 v dpclk5 (3) v dpclk6 v dpclk7 v notes to ta b l e 2 ? 7 : (1) ep1c3 devices only have one pll (pll 1). (2) ep1c3 devices in the 100-pin tqfp package do not have dedicated clock pins clk1 and clk3 . (3) ep1c3 devices in the 100-pin tqfp package do not have the dpclk0 , dpclk1 , or dpclk5 pins. table 2?7. global clock network sources (part 2 of 2) source gclk0 gclk1 gclk2 gclk3 gclk4 gclk5 gclk6 gclk7
2?36 altera corporation preliminary january 2007 cyclone device handbook, volume 1 external clock inputs each pll supports single-ended or differential inputs for source- synchronous receivers or for genera l-purpose use. the dedicated clock pins ( clk[3..0] ) feed the pll inputs. these dual-purpose pins can also act as lvds input pins. see figure 2?25 . table 2?8 shows the i/o standards support ed by pll input and output pins. for more information on lvds i/o support, see ?lvds i/o pins? on page 2?54 . external clock outputs each pll supports one differential or one single-ended output for source- synchronous transmitters or for gene ral-purpose external clocks. if the pll does not use these pll_out pins, the pins are available for use as general-purpose i/o pins. the pll_out pins support all i/o standards shown in table 2?8 . the external clock outputs do not have their own v cc and ground voltage supplies. therefore, to minimize jitte r, do not place switching i/o pins next to these output pins. the ep1c 3 device in the 100-pin tqfp package table 2?8. pll i/o standards i/o standard clk input extclk output 3.3-v lvttl/lvcmos vv 2.5-v lvttl/lvcmos vv 1.8-v lvttl/lvcmos vv 1.5-v lvcmos vv 3.3-v pci vv lv d s vv sstl-2 class i vv sstl-2 class ii vv sstl-3 class i vv sstl-3 class ii vv differential sstl-2 v
altera corporation 2?37 january 2007 preliminary global clock network & phase-locked loops does not have dedicated clock output pins. the ep1c6 device in the 144-pin tqfp package only support s dedicated clock outputs from pll 1. clock feedback cyclone plls have three modes for mul tiplication and/or phase shifting: zero delay buffer mode ? the external clock output pin is phase- aligned with the clock input pin for zero delay. normal mode ? if the design uses an internal pll clock output, the normal mode compensates for the in ternal clock delay from the input clock pin to the ioe registers. the ex ternal clock output pin is phase shifted with respect to the clock inpu t pin if connected in this mode. you defines which internal clock output from the pll should be phase-aligned to compensate for internal clock delay. no compensation mode ? in this mode, the pll will not compensate for any clock networks. phase shifting cyclone plls have an advanced cl ock shift capability that enables programmable phase shifts. you can enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. you can perform phase shifti ng in time units with a resolution range of 125 to 250 ps. the finest resolu tion equals one eighth of the vco period. the vco period is a functi on of the frequency input and the multiplication and division factors. each clock output counter can choose a different phase of the vco period fr om up to eight taps. you can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase-shift range for the entire period of the output clock. the phase tap feedback to the m counter can shift all outputs to a single phase. the quartus ii software automatically sets the phase taps and counter settings according to the phase shift entered. lock detect signal the lock output indicates that there is a stable clock output signal in phase with the reference clock. withou t any additional ci rcuitry, the lock signal may toggle as the pll begins tracking the reference clock. therefore, you may need to gate the lock signal for use as a system- control signal. for correct operation of the lock circuit below ?20 c, f in/n > 200 mhz.
2?38 altera corporation preliminary january 2007 cyclone device handbook, volume 1 programmable duty cycle the programmable duty cycle allows pl ls to generate clock outputs with a variable duty cycle. this feature is supported on each pll post-scale counter (g0, g1, e). the duty cycle setti ng is achieved by a low- and high- time count setting for the post-scale dividers. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. control signals there are three control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and the ability to gate pll output cl ocks for low-power applications. the pllenable signal enables and di sables plls. when the pllenable signal is low, the clock output ports are driven by ground and all the plls go out of lock. when the pllenable signal goes high again, the plls relock and resynchronize to the input clocks. an input pin or le output can drive the pllenable signal. the areset signals are reset/resynchronization inputs for each pll. cyclone devices can drive these input signals from input pins or from les. when areset is driven high, the pll counters will reset, clearing the pll output and placing the pll ou t of lock. when driven low again, the pll will resynchronize to its input as it relocks. the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you di sable the pfd, the vco will operate at its last set value of control voltage and frequency with some drift, and the system will continue running when the pll goes out of lock or the input clock disables. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you can either use their own control signal or gated locked status signals to trigger the pfdena signal. f for more information on cyclone plls, see chapter 6, using plls in cyclone devices .
altera corporation 2?39 january 2007 preliminary i/o structure i/o structure ioes support many features, including: differential and single-ended i/o standards 3.3-v, 64- and 32-bit, 66- and 33-mhz pci compliance joint test action group (jtag) boundary-scan test (bst) support output drive strength control weak pull-up resistors during configuration slew-rate control tri-state buffers bus-hold circuitry programmable pull-up resistors in user mode programmable input and output delays open-drain outputs dq and dqs i/o pins cyclone device ioes contain a bidirectional i/o buffer and three registers for complete embedded bidirectional single data rate transfer. figure 2?27 shows the cyclone ioe structur e. the ioe contains one input register, one output register, and one output enable register. you can use the input registers for fast setup time s and output registers for fast clock- to-output times. additional ly, you can use the output enable (oe) register for fast clock-to-output enable timing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. ioes can be used as input, output, or bidirectional pins.
2?40 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?27. cyclone ioe structure note to figure 2?27 : (1) there are two paths available for combinatorial inputs to the logic array. each path contains a unique programmable delay chain. the ioes are located in i/o blocks around the periphery of the cyclone device. there are up to three ioes per row i/o block and up to three ioes per column i/o block (column i/o blocks span two columns). the row i/o blocks drive row, column, or dire ct link interconnects. the column i/o blocks drive column interconnects. figure 2?28 shows how a row i/o block connects to the logic array. figure 2?29 shows how a column i/o block connects to the logic array. output register output combinatorial input (1) input oe register oe input register logic array dq dq dq
altera corporation 2?41 january 2007 preliminary i/o structure figure 2?28. row i/o block c onnection to the interconnect notes to figure 2?28 : (1) the 21 data and control signal s consist of three data out lines, io_dataout[2..0] , three output enables, io_coe[2..0] , three input clock enables, io_cce_in[2..0] , three output clock enables, io_cce_out[2..0] , three clocks, io_cclk[2..0] , three asynchronous clear signals, io_caclr[2..0] , and three synchronous clear signals, io_csclr[2..0] . (2) each of the three ioes in the row i/o block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. 21 r4 interconnects c4 interconnects i/o block local interconnect 21 data and control signals from logic array (1 ) io_datain[2..0] and comb_io_datain[2..0] (2) io_clk[5:0] row i/o block contains up to three ioes direct link interconnect to adjacent lab direct link interconnect from adjacent lab lab local interconnect lab row i/o block
2?42 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?29. column i/o block connection to the interconnect notes to figure 2?29 : (1) the 21 data and control signal s consist of three data out lines, io_dataout[2..0] , three output enables, io_coe[2..0] , three input clock enables, io_cce_in[2..0] , three output clock enables, io_cce_out[2..0] , three clocks, io_cclk[2..0] , three asynchronous clear signals, io_caclr[2..0] , and three synchronous clear signals, io_csclr[2..0] . (2) each of the three ioes in th e column i/o block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. 21 data & control signals from logic array (1) column i/o block contains up to three ioe s i/o block local interconnect io_datain[2:0] & comb_io_datain[2..0] (2) r4 interconnects lab local interconnect c4 interconnects 21 lab lab lab io_clk[5..0] column i/o block
altera corporation 2?43 january 2007 preliminary i/o structure the pin's datain signals can drive the logic array. the logic array drives the control and data signals, providing a flexible routing resource. the row or column ioe clocks, io_clk[5..0] , provide a dedicated routing resource for low-skew, high-speed clocks. the global clock network generates the ioe clocks that feed the row or column i/o regions (see ?global clock network & phase-locked loops? on page 2?29 ). figure 2?30 illustrates the signal pa ths through the i/o block. figure 2?30. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr / preset , sclr / preset , clk_in , and clk_out . figure 2?31 illustrates the control signal selection. row or column io_clk[5..0] io_datain comb_io_datain io_dataout io_coe oe ce_in ce_out io_cce_in aclr/preset io_cce_out sclr io_caclr clk_in io_cclk clk_out dataout data and control signal selection ioe to logic array from logic array to other ioes io_csclr
2?44 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 2?31. control signal selection per ioe in normal bidirectional operation, you can use the input register for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. the oe register is available for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from the lo cal interconnect in the associated lab, dedicated i/o clocks, or th e column and row interconnects. figure 2?32 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset dedicated i/o clock [5..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_caclr local interconnect io_csclr io_cce_out io_cce_in io_cclk
altera corporation 2?45 january 2007 preliminary i/o structure figure 2?32. cyclone ioe in bidire ctional i/o configuration the cyclone device ioe includes programmable delays to ensure zero hold times, minimi ze setup times, or increa se clock to output times. a path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. programmable delays decrea se input-pin-to-logic-array and ioe input register delays. the quartus ii compiler can program these delays chip-wide reset oe register v ccio optio n al pci clamp col u mn or ro w interconect ioe_clk[5..0] inp u t register inp u t pin to inp u t register delay or inp u t pin to logic array delay inp u t pin to logic array delay dri v e strength control open-drain o u tp u t sle w control sclr/preset oe clko u t ce_o u t aclr/prn clkin ce_in p r og r ammabl e pull-up re s i s to r bu s hold prn clrn dq o u tp u t register prn clrn dq prn clrn dq v ccio com b _datain data_in ena ena ena o u tp u t pin delay
2?46 altera corporation preliminary january 2007 cyclone device handbook, volume 1 to automatically minimize setup time while providing a zero hold time. programmable delays can increase the register-to-pin delays for output registers. table 2?9 shows the programmable delays for cyclone devices. there are two paths in the ioe for a combinatorial input to reach the logic array. each of the two paths can have a different delay. this allows you adjust delays from the pin to internal le registers that reside in two different areas of the device. the designer sets the two combinatorial input delays by selecting different delays for two different paths under the decrease input delay to internal cells logic option in the quartus ii software. when the input signal requires two different delays for the combinatorial input, the input register in the ioe is no longer available. the ioe registers in cyclone devices share the same source for clear or preset. the designer can program preset or clear for each individual ioe. the designer can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the re gisters. if programmed to power up high, an asynchronous preset can co ntrol the registers. this feature prevents the inadvertent activation of another de vice's active-low input upon power up. if one register in an io e uses a preset or clear signal then all registers in the ioe must use that sa me signal if they require preset or clear. additionally a sync hronous reset signal is available to the designer for the ioe registers. external ram interfacing cyclone devices support ddr sdram and fcram interfaces at up to 133 mhz through dedicated circuitry. ddr sdram & fcram cyclone devices have dedicated circuitry for interfacing with ddr sdram. all i/o banks support ddr sdram and fcram i/o pins. however, the configuration input pins in bank 1 must operate at 2.5 v because the sstl-2 v ccio level is 2.5 v. additionally, the configuration table 2?9. cyclone programmable delay chain programmable delays quartus ii logic option input pin to logic array delay decrease input delay to internal cells input pin to input register delay decr ease input delay to input registers output pin delay increase delay to output pin
altera corporation 2?47 january 2007 preliminary i/o structure output pins ( nstatus and conf_done ) and all the jtag pins in i/o bank 3 must operate at 2.5 v because the v ccio level of sstl-2 is 2.5 v. i/o banks 1, 2, 3, and 4 support dqs signals with dq bus modes of 8. for 8 mode, there are up to eight groups of programmable dqs and dq pins, i/o banks 1, 2, 3, and 4 each have two groups in the 324-pin and 400-pin fineline bga packages. each gr oup consists of one dqs pin, a set of eight dq pins, and one dm pin (see figure 2?33 ). each dqs pin drives the set of eight dq pins within that group. figure 2?33. cyclone device dq & dqs groups in 8 mode note (1) note to figure 2?33 : (1) each dq group consists of one dqs pin, eight dq pins, and one dm pin. table 2?10 shows the number of dq pin groups per device. dq pins dqs pin dm pin top, bottom, left, or right i/o bank table 2?10. dq pin groups (part 1 of 2) device package number of 8 dq pin groups total dq pin count ep1c3 100-pin tqfp (1) 324 144-pin tqfp 4 32 ep1c4 324-pin fineline bga 8 64 400-pin fineline bga 8 64
2?48 altera corporation preliminary january 2007 cyclone device handbook, volume 1 a programmable delay chain on each dqs pin allows for either a 90 phase shift (for ddr sdram), or a 72 phase shift (for fcram) which automatically center-aligns input dqs synchronization signals within the data window of their corresponding dq data signals. the phase-shifted dqs signals drive the global clock network. this gl obal dqs signal clocks dq signals on internal le registers. these dqs delay elements combine wi th the pll?s clocking and phase shift ability to provide a complete hardware solution for interfacing to high-speed memory. the clock phase shift allo ws the pll to clock the dq output enable and output paths. the design er should use the following guidelines to meet 133 mhz performance for ddr sdram and fcram interfaces: the dqs signal must be in the mi ddle of the dq group it clocks resynchronize the incoming data to the logic array clock using successive le registers or fifo buffers le registers must be placed in th e lab adjacent to the dq i/o pin column it is fed by figure 2?34 illustrates ddr sdram and fcram interfacing from the i/o through the dedicated ci rcuitry to the logic array. ep1c6 144-pin tqfp 4 32 240-pin pqfp 4 32 256-pin fineline bga 4 32 ep1c12 240-pin pqfp 4 32 256-pin fineline bga 4 32 324-pin fineline bga 8 64 ep1c20 324-pin fineline bga 8 64 400-pin fineline bga 8 64 note to table 2?10 : (1) ep1c3 devices in the 100-pin tqfp package do not have any dq pin groups in i/o bank 1. table 2?10. dq pin groups (part 2 of 2) device package number of 8 dq pin groups total dq pin count
altera corporation 2?49 january 2007 preliminary i/o structure figure 2?34. ddr sdram & fcram interfacing programmable drive strength the output buffer for each cyclone device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl and lvcmos standards have seve ral levels of drive strength that the designer can control. sstl-3 class i and ii, and sstl-2 class i and ii support a minimum setting, the lowest drive strength that guarantees the i oh /i ol v cc gnd pll phase shifted -90 ? dqs adjacent lab les global clock resynchronizing global clock programmable delay chain output le register output le registers dq input le registers input le registers le register le register t adjacent lab les oe oe le register oe le register oe oe le register oe le register output le registers output le register dataa datab clk -90? clk
2?50 altera corporation preliminary january 2007 cyclone device handbook, volume 1 of the standard. using minimum sett ings provides signal slew rate control to reduce system noise and signal overshoot. table 2?11 shows the possible settings for the i/o standa rds with drive strength control. open-drain output cyclone devices provide an optional open-drain (e quivalent to an open- collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asse rted by any of several devices. table 2?11. programmable drive strength note (1) i/o standard i oh /i ol current strength setting (ma) lvttl (3.3 v) 4 8 12 16 24 (2) lvcmos (3.3 v) 2 4 8 12 (2) lvttl (2.5 v) 2 8 12 16 (2) lvttl (1.8 v) 2 8 12 (2) lvcmos (1.5 v) 2 4 8 (2) notes to ta b l e 2 ? 11 : (1) sstl-3 class i and ii, sstl-2 class i an d ii, and 3.3-v pci i/o standards do not support programmable drive strength. (2) this is the default current strength setting in the quartus ii software.
altera corporation 2?51 january 2007 preliminary i/o structure slew-rate control the output buffer for each cyclone device i/o pin has a programmable output slew-rate control that can be configured for low noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. howeve r, these fast transitions may introduce noise transien ts into the system. a slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. each i/o pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. the slew-rate control affects both the rising and falling edges. bus hold each cyclone device i/o pin provides an optional bus-ho ld feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. the designer can select this feature individually for each i/o pin. the bus-hold output will drive no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the device cannot use the programmable pull-up option. disable the bus-hold feature when the i/o pin is configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (rbh) of approximately 7 k to pull the signal level to the last-driven state. table 4?15 on page 4?6 gives the specific sustaining current for each v ccio voltage level driven through this resistor and overdrive current used to identify the next-driven input level. the bus-hold circuitry is only active after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. programmable pull-up resistor each cyclone device i/o pin provides an optional programmable pull- up resistor during user mode. if the designer enables this feature for an i/o pin, the pull-up resistor (typically 25 k ) holds the output to the v ccio level of the output pin's bank. de dicated clock pins do not have the optional programmable pull-up resistor.
2?52 altera corporation preliminary january 2007 cyclone device handbook, volume 1 advanced i/o standard support cyclone device ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci lvds rsds sstl-2 class i and ii sstl-3 class i and ii differential sstl-2 class ii (on output clocks only) table 2?12 describes the i/o standards supported by cyclone devices. cyclone devices contain four i/o banks, as shown in figure 2?35 . i/o banks 1 and 3 support all th e i/o standards listed in table 2?12 . i/o banks 2 and 4 support all the i/o standards listed in table 2?12 except the 3.3-v pci standard. i/o banks 2 and 4 contain dual-purpose dqs, dq, table 2?12. cyclone i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) 3.3-v lvttl/lvcmos single-ended n /a 3.3 n /a 2.5-v lvttl/lvcmos single-ended n /a 2.5 n /a 1.8-v lvttl/lvcmos single-ended n /a 1.8 n /a 1.5-v lvcmos single-ended n /a 1.5 n /a 3.3-v pci (1) single-ended n /a 3.3 n /a lv d s (2) differential n /a 2.5 n /a rsds (2) differential n /a 2.5 n /a sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 sstl-3 class i and ii voltage-referenced 1.5 3.3 1.5 differential sstl-2 (3) differential 1.25 2.5 1.25 notes to table 2?12 : (1) there is no megafunction support for ep1c3 devices for the pci compiler. however, ep1c3 devices support pci by using the lvttl 16-ma i/o standard and drive strength assignments in the quartus ii software. the device requires an external dio de for pci compliance. (2) ep1c3 devices in the 100-pin tqfp package do not support the lvds and rsds i/o standards. (3) this i/o standard is only available on output clock pins ( pll_out pins). ep1c3 devices in the 100-pin package do not support this i/o standa rd as it does not have pll_out pins.
altera corporation 2?53 january 2007 preliminary i/o structure and dm pins to support a ddr sdra m or fcram interface. i/o bank 1 can also support a ddr sdram or fcram interface, however, the configuration input pins in i/o bank 1 must operate at 2.5 v. i/o bank 3 can also support a ddr sdram or fc ram interface, however, all the jtag pins in i/o bank 3 must operate at 2.5 v. figure 2?35. cycl one i/o banks notes (1) , (2) notes to figure 2?35 : (1) figure 2?35 is a top view of the silicon die. (2) figure 2?35 is a graphic representation only. refer to the pin li st and the quartus ii software for exact pin locations. each i/o bank has its own vccio pins. a single device can support 1.5-v, 1.8-v, 2.5-v, and 3.3-v interfaces; each individual bank can support a different standard with different i/o voltages. each bank also has dual- purpose vref pins to support any one of the voltage-referenced standards (e.g., sstl-3) independently. if an i/o bank does not use voltage-referenced standards, the v ref pins are available as user i/o pins. i/ o ba nk 2 i/ o ba nk 3 i/ o ba nk 4 i/ o ba nk 1 all i/ o ba nk s s u pp o rt 3 . 3 -v lvttl/lv cmos 2 . 5 -v lvttl/lv cmos 1.8-v lvttl/lv cmos 1. 5 -v lv cmos lv ds rsds ss tl- 2 c l ass i a n d ii ss tl- 3 c l ass i a n d ii i/ o ba nk 3 al s o s u pp o rt s t h e 3 . 3 -v pc i i/ o sta n dard i/ o ba nk 1 al s o s u pp o rts t h e 3 . 3 -v pc i i/ o sta n dard in d ivi d u a l p ow er b u s
2?54 altera corporation preliminary january 2007 cyclone device handbook, volume 1 each i/o bank can support multiple standards with the same v ccio for input and output pins. for example, when v ccio is 3.3-v, a bank can support lvttl, lvcmos, 3.3-v pci, and sstl-3 for inputs and outputs. lvds i/o pins a subset of pins in all four i/o banks supports lvds interfacing. these dual-purpose lvds pins require an external-resistor network at the transmitter channels in addition to 100- termination resistors on receiver channels. these pins do not contain dedica ted serialization or deserialization circuitry; therefore, internal logic perf orms serialization and deserialization functions. table 2?13 shows the total number of su pported lvds channels per device density. multivolt i/o interface the cyclone architecture supports th e multivolt i/o interface feature, which allows cyclone devices in all packages to interface with systems of different supply voltages. the devices have one set of v cc pins for internal operation and input buffers (v ccint ), and four sets for i/o output drivers (v ccio ). table 2?13. cyclone device lvds channels device pin count number of lvds channels ep1c3 100 (1) 144 34 ep1c4 324 103 400 129 ep1c6 144 29 240 72 256 72 ep1c12 240 66 256 72 324 103 ep1c20 324 95 400 129 note to table 2?13 : (1) ep1c3 devices in the 100-pin tqfp package do not support the lvds i/o standard.
altera corporation 2?55 january 2007 preliminary power sequencing & hot socketing the cyclone v ccint pins must always be connected to a 1.5-v power supply. if the v ccint level is 1.5 v, then input pi ns are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the v ccio pins can be connected to either a 1.5-v, 1.8-v, 2.5-v, or 3.3-v power supply, depend ing on the output requirements. the output levels are compatible with systems of the same voltage as the power supply (i.e., when v ccio pins are connected to a 1.5-v power supply, the output levels are compat ible with 1.5-v systems). when v ccio pins are connected to a 3.3-v power su pply, the output high is 3.3-v and is compatible with 3.3-v or 5.0-v systems. table 2?14 summarizes cyclone multivolt i/o support. power sequencing & hot socketing because cyclone devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. therefore, the v ccio and v ccint power supplies may be powered in any order. signals can be driven into cyclone devices before and during power up without damaging the device. in addi tion, cyclone devices do not drive out during power up. once operating conditions are reached and the device is configured, cyclone device s operate as specified by the user. table 2?14. cyclone mul tivolt i/o support note (1) v ccio (v) input signal output signal 1.5 v1.8 v2.5 v3.3 v5.0 v1.5 v1.8 v2.5 v3.3 v5.0 v 1.5 vv v (2) v (2) v 1.8 vv v (2) v (2) v (3) v 2.5 vv v (5) v (5) v 3.3 v (4) v v (6) v (7) v (7) v (7) v v (8) notes to table 2?14 : (1) the pci clamping diode must be disabled to drive an input with voltages higher than v ccio . (2) when v ccio = 1.5-v or 1.8-v and a 2.5-v or 3.3-v input signal feeds an input pin, higher pin leakage current is expected. turn on allow voltage overdrive for lvttl / lvcmos input pins in the assignments > device > device and pin options > pin placement tab when a device has this i/o combinations. (3) when v ccio = 1.8-v, a cyclone device can drive a 1.5-v device with 1.8-v tolerant inputs. (4) when v ccio = 3.3-v and a 2.5-v input signal feeds an input pin, the v ccio supply current will be slightly larger than expected. (5) when v ccio = 2.5-v, a cyclone device can drive a 1.5-v or 1.8-v device with 2.5-v tolerant inputs. (6) cyclone devices can be 5.0-v tolerant with the use of an external resistor and the internal pci clamp diode. (7) when v ccio = 3.3-v, a cyclone device can drive a 1.5-v, 1.8-v, or 2.5-v device with 3.3-v tolerant inputs. (8) when v ccio = 3.3-v, a cyclone device can drive a device with 5.0-v lvttl inputs but not 5.0-v lvcmos inputs.
2?56 altera corporation preliminary january 2007 cyclone device handbook, volume 1 document revision history table 2?15 shows the revision history for this document. table 2?15. document revision history date & document version changes made summary of changes january 2007 v1.5 added document revision history. updated figures 2?17 , 2?18 , 2?19 , 2?20 , 2?21 , and 2?32 . august 2005 v1.4 minor updates. february 2005 v1.3 updated jtag chain limits. added test vector information. corrected figure 2-12. added a note to tables 2-17 through 2-21 regarding violating the setup or hold time. october 2003 v1.2 updated phase shift information. added 64-bit pci support information. september 2003 v1.1 updated lvds data rates to 640 mbps from 311 mbps. may 2003 v1.0 added document to cyclone device handbook.
altera corporation 3?1 january 2007 preliminary 3. configuration & testing ieee std. 1149.1 (jtag) boundary scan support all cyclone ? devices provide jtag bst circ uitry that comp lies with the ieee std. 1149.1a-1990 spec ification. jtag boundary-scan testing can be performed either before or after, bu t not during configuration. cyclone devices can also use the jtag port fo r configuration together with either the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). cyclone devices support reconfigurin g the i/o standard settings on the ioe through the jtag bst chain. th e jtag chain can update the i/o standard for all input and output pins any time before or during user mode. designers can use this ability fo r jtag testing before configuration when some of the cyclone pins drive or receive from other devices on the board using voltage-referenced standards. since the cyclone device might not be configured before jtag testing, the i/o pins might not be configured for appropriate electrical standards for chip-to-chip communication. programming those i/o standards via jtag allows designers to fully test i/o connection to other devices. the jtag pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the tdo pin voltage is determined by the v ccio of the bank where it resides. the bank v ccio selects whether the jtag inputs are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. cyclone devices also use the jtag po rt to monitor the operation of the device with the signaltap ? ii embedded logic analyzer. cyclone devices support the jtag instructions shown in table 3?1 . table 3?1. cyclone jtag instructions (part 1 of 2) jtag instruction instr uction code description sample / preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 0000 allows the external circui try and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. c51003-1.3
3?2 altera corporation preliminary january 2007 cyclone device handbook, volume 1 in the quartus ii software, there is an auto usercode feature where you can choose to use the checksum value of a programming file as the jtag user code. if selected, the checks um is automatically loaded to the usercode register. choose assignments > device > device and pin options > general. turn on auto usercode . usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the userco de to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. icr instructions used when configuring a cy clone device via the jtag port with a masterblaster tm or byteblastermv tm download cable, or when using a jam file or jam byte-code file via an embedded processor. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, after, or during configuration. stops configuration if executed during configuration. once issued, the config_io instruction will hold nstatus low to reset the configuration device. nstatus is held low until the device is reconfigured. signaltap ii instructions monitors internal device operation with the signaltap ii embedded logic analyzer. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . table 3?1. cyclone jtag instructions (part 2 of 2) jtag instruction instr uction code description
altera corporation 3?3 january 2007 preliminary ieee std. 1149.1 (jtag) boundary scan support the cyclone device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for cyclone devices. table 3?2. cyclone boundary- scan register length device boundary-scan register length ep1c3 339 ep1c4 930 ep1c6 582 ep1c12 774 ep1c20 930 table 3?3. 32-bit cyclone device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep1c3 0000 0010 0000 1000 0001 000 0110 1110 1 ep1c4 0000 0010 0000 1000 0101 000 0110 1110 1 ep1c6 0000 0010 0000 1000 0010 000 0110 1110 1 ep1c12 0000 0010 0000 1000 0011 000 0110 1110 1 ep1c20 0000 0010 0000 1000 0100 000 0110 1110 1 notes to ta b l e 3 ? 3 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1 .
3?4 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 3?1 shows the timing requirements for the jtag signals. figure 3?1. cyclone jtag waveforms table 3?4 shows the jtag timing parame ters and values for cyclone devices. table 3?4. cyclone jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
altera corporation 3?5 january 2007 preliminary signaltap ii embedded logic analyzer 1 cyclone devices must be within the first 8 devices in a jtag chain. all of these devices have the same jtag controller. if any of the cyclone devices are in the 9th or after they will fail configuration. this does not affect the signaltap ? ii logic analyzer. f for more information on jtag, see the following documents: an 39: ieee std. 1149.1 (jtag) boun dary-scan testing in altera devices jam programming & test language specification signaltap ii embedded logic analyzer cyclone devices feature the signaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. a designer can analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconne cts in the cyclone architecture are configured with cmos sram elements. altera fpgas are reconfigurable and every device is tested with a high coverage production test program so the desi gner does not have to perform fault testing and can instead focus on simulation and design verification. cyclone devices are configured at syst em power-up with data stored in an altera configuration device or provided by a system controller. the cyclone device's optimize d interface allows the device to act as controller in an active serial configuration sc heme with the new low-cost serial configuration device. cyclone devices can be configured in under 120 ms using serial data at 20 mhz. the serial configuration device can be programmed via the byteblaster ii download cable, the altera programming unit (apu), or third-party programmers. in addition to the new low-cost serial configuration device, altera offers in-system programmability (isp)-capab le configuration devices that can configure cyclone devices via a serial data stream. the interface also enables microprocessors to treat cyclone devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. after a cyclone device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. real-time changes can be made du ring system operation, enabling innovative reconfigurable computing applications.
3?6 altera corporation preliminary january 2007 cyclone device handbook, volume 1 operating modes the cyclone architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sr am data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allow cyclone devices to be reconfigured in-circuit by loading new configuratio n data into the device. with real- time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. designers can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. a built-in weak pull-up resistor pulls all user i/o pins to v ccio before and during device configuration. the configuration pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the voltage level of the configuration output pins is determined by the v ccio of the bank where the pins reside. the bank v ccio selects whether the configuration in puts are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. configuration schemes designers can load the configuration data for a cyclone device with one of three configuration schemes (see table 3?5 ), chosen on the basis of the target application. designers can us e a configuration device, intelligent controller, or the jtag port to configure a cyclone device. a low-cost configuration device can automatically configure a cyclone device at system power-up.
altera corporation 3?7 january 2007 preliminary document revision history multiple cyclone devices can be configured in any of the three configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. document revision history table 3?6 shows the revision history for this document. table 3?5. data sources for configuration configuration scheme data source active serial low-cost serial configuration device passive serial (ps) enhanced or epc2 configuration device, masterblaster or byteblastermv download cable, or serial data source jtag masterblaster or byteblastermv download cable or a microprocessor with a jam or jbc file table 3?6. document revision history date & document version changes made summary of changes january 2007 v1.3 added document revision history. updated handpara note below ta b l e 3 ? 4 . august 2005 v1.2 minor updates. february 2005 v1.1 updated jtag chain limits. added information concerning test vectors. may 2003 v1.0 added document to cyclone device handbook.
3?8 altera corporation preliminary january 2007 cyclone device handbook, volume 1
altera corporation 4?1 january 2007 preliminary 4. dc & switching characteristics operating conditions cyclone ? devices are offered in both commercial, industrial, and extended temperature grades. however, industrial-grade and extended- temperature-grade devices may have limited speed-grade availability. tables 4?1 through 4?16 provide information on absolute maximum ratings, recommended operating cond itions, dc operating conditions, and capacitance for cyclone devices. table 4?1. cyclone device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v cci n t supply voltage w ith respect to ground (3) ?0.5 2.4 v v ccio ?0.5 4.6 v v cca supply voltage w ith respect to ground (3) ?0.5 2.4 v v i dc input voltage ?0.5 4.6 v i out dc output current, per pin ?25 25 ma t stg storage temperature n o bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature bga packages under bias 135 c table 4?2. cyclone device recommended operating conditions (part 1 of 2) symbol parameter conditions minimum maximum unit v cci n t supply voltage for internal logic and input buffers (4) 1.425 1.575 v v ccio supply voltage for output buffers, 3.3-v operation (4) 3.00 3.60 v supply voltage for output buffers, 2.5-v operation (4) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (4) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (4) 1.4 1.6 v v i input voltage (3) , (5) ?0.5 4.1 v c51004-1.6
4?2 altera corporation preliminary january 2007 cyclone device handbook, volume 1 v o output voltage 0 v ccio v t j operating junction temperature for commercial use 085 c for industrial use ?40 100 c for extended- temperature use ?40 125 c table 4?3. cyclone device dc operating conditions note (6) symbol parameter conditions minimum typica l maximum unit i i input pin leakage current v i = v cciomax to 0 v (8) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (8) ?10 10 a i cc0 v cc supply current (standby) (all m4k blocks in power-down mode) (7) ep1c3 4 ma ep1c4 6 ma ep1c6 6 ma ep1c12 8 ma ep1c20 12 ma r co n f (9) value of i/o pin pull-up resistor before and during configuration v i = 0 v; v cci0 = 3.3 v 15 25 50 k v i = 0 v; v cci0 = 2.5 v 20 45 70 k v i = 0 v; v cci0 = 1.8 v 30 65 100 k v i = 0 v; v cci0 = 1.5 v 50 100 150 k recommended value of i/o pin external pull-down resistor before and during configuration 12k table 4?4. lvttl specifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v table 4?2. cyclone device recommended operating conditions (part 2 of 2) symbol parameter conditions minimum maximum unit
altera corporation 4?3 january 2007 preliminary operating conditions v oh high-level output voltage i oh = ?4 to ?24 ma (11) 2.4 v v ol low-level output voltage i ol = 4 to 24 ma (11) 0.45 v table 4?5. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma 0.2 v table 4?6. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?0.1 ma 2.1 v i oh = ?1 ma 2.0 v i oh = ?2 to ?16 ma (11) 1.7 v v ol low-level output voltage i ol = 0.1 ma 0.2 v i oh = 1 ma 0.4 v i oh = 2 to 16 ma (11) 0.7 v table 4?4. lvttl specifications (part 2 of 2) symbol parameter conditions minimum maximum unit
4?4 altera corporation preliminary january 2007 cyclone device handbook, volume 1 table 4?7. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.65 1.95 v v ih high-level input voltage 0.65 v ccio 2.25 (12) v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 to ?8 ma (11) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 to 8 ma (11) 0.45 v table 4?8. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.4 1.6 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 (12) v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (11) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (11) 0.25 v ccio v table 4?9. 2.5-v lvds i/o specifications note (13) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 2.375 2.5 2.625 v v od differential output voltage r l = 100 250 550 mv v od change in v od between high and low r l = 100 50 mv v os output offset voltage r l = 100 1.125 1.25 1.375 v v os change in v os between high and low r l = 100 50 mv v th differential input threshold v cm = 1.2 v ?100 100 mv v i n receiver input voltage range 0.0 2.4 v r l receiver differential input resistor 90 100 110
altera corporation 4?5 january 2007 preliminary operating conditions table 4?10. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 4?11. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih high-level input voltage v ref + 0.18 3.0 v v il low-level input voltage ?0.3 v ref ? 0.18 v v oh high-level output voltage i oh = ?8.1 ma (11) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (11) v tt ? 0.57 v table 4?12. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.3 2.5 2.7 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih high-level input voltage v ref + 0.18 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.18 v v oh high-level output voltage i oh = ?16.4 ma (11) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (11) v tt ? 0.76 v
4?6 altera corporation preliminary january 2007 cyclone device handbook, volume 1 table 4?13. sstl-3 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih high-level input voltage v ref + 0.2 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (11) v tt + 0.6 v v ol low-level output voltage i ol = 8 ma (11) v tt ? 0.6 v table 4?14. sstl-3 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih high-level input voltage v ref + 0.2 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (11) v tt + 0.8 v v ol low-level output voltage i ol = 16 ma (11) v tt ? 0.8 v table 4?15. bus hold parameters parameter conditions v ccio level unit 1.5 v1.8 v2.5 v3.3 v min max min max min max min max low sustaining current v i n > v il (maximum) 30 50 70 a high sustaining current v i n < v ih (minimum) ?30 ?50 ?70 a low overdrive current 0 v < v i n < v ccio 200 300 500 a high overdrive current 0 v < v i n < v ccio ?200 ?300 ?500 a
altera corporation 4?7 january 2007 preliminary operating conditions table 4?16. cyclone device capacitance note (14) symbol parameter typical unit c io input capacitance for user i/o pin 4.0 pf c lv d s input capacitance for dual-purpose lvds/user i/o pin 4.7 pf c vref input capacitance for dual-purpose v ref /user i/o pin. 12.0 pf c dpclk input capacitance for dual-purpose dpclk /user i/o pin. 4.4 pf c clk input capacitance for clk pin. 4.7 pf notes to ta b l e s 4 ? 1 through 4?16 : (1) refer to the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) minimum dc input is ?0.5 v. during transitions, the in puts may undershoot to ?2.0 v or overshoot to 4.6 v for input currents less than 100 ma and periods shorter than 20 ns. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (6) typical values are for t a = 25 c, v ccint = 1.5 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (7) v i = ground, no load, no toggling inputs. (8) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (9) r conf is the measured value of internal pull-up resistan ce when the i/o pin is tied directly to gnd. r conf value will be lower if an external source drives the pin higher than v ccio . (10) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (11) drive strength is programm able according to values in chapter 2, cyclone architecture , table 2?11 . (12) overdrive is possible when a 1.5 v or 1.8 v and a 2.5 v or 3.3 v input signal feeds an input pin. turn on ?allow voltage overdrive? for lvttl/lvcmos input pins in th e assignments > device > device and pin options > pin placement tab when a device has this i/o combination. however, higher leakage current is expected. (13) the cyclone lvds interface requires a resist or network outside of th e transmitter channels. (14) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf.
4?8 altera corporation preliminary january 2007 cyclone device handbook, volume 1 power consumption designers can use the altera web ea rly power estimator to estimate the device power. cyclone devices require a certain amount of power-up current to successfully power up because of the nature of the leading-edge process on which they are fabricated. table 4?17 shows the maximum power-up current required to power up a cyclone device. designers should select power supplies and regulators that can supply this amount of current when desi gning with cyclone devices. this specification is for commercial operating conditions. measurements were performed with an isolated cyclon e device on the board. decoupling capacitors were not used in this measur ement. to factor in the current for decoupling capacitors, sum up the cu rrent for each capacitor using the following equation: i = c (dv/dt) the exact amount of current that is consumed varies according to the process, temperature, and power ramp rate. if the power supply or regulator can supply more current than required, the cyclone device may consume more current than the maximum current specified in table 4?17 . however, the device does not requir e any more current to successfully power up than what is listed in table 4?17 . the duration of the i ccint power-up requirement depends on the v ccint voltage supply rise time. the power-up current consumption drops when the v ccint supply reaches approximately 0.75 v. for example, if the v ccint rise time has a linear rise of 15 ms, the current consumption spike drops by 7.5 ms. table 4?17. cyclone maximum power-up current (i ccint ) requirements (in-rush current) device commercial specification industrial specification unit ep1c3 150 180 ma ep1c4 150 180 ma ep1c6 175 210 ma ep1c12 300 360 ma ep1c20 500 600 ma notes to table 4?17 : (1) the cyclone devices (except for the ep1c20 devi ce) meet the power up specification for mini pci. (2) the lot codes 9g0082 to 9g2999, or 9g3109 and later comply to the specifications in table 4?17 and meet the mini pci specification. lot codes appear at the top of the device. (3) the lot codes 9h0004 to 9h29999, or 9h3014 and later comply to the specifications in this table and meet the mini pci specification. lot codes appear at the top of the device.
altera corporation 4?9 january 2007 preliminary timing model typically, the user-mode current duri ng device operation is lower than the power-up current in table 4?17 . altera recommends using the cyclone power calculator, available on the altera web site, to estimate the user-mode i ccint consumption and then se lect power supplies or regulators based on the higher value. timing model the directdrive technology and mu ltitrack interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across all cyclone device densities and speed grades. this section describes and specifies the pe rformance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. preliminary & final timing timing models can have either preliminary or final status. the quartus ? ii software issues an informational message during the design compilation if the timing models are preliminary. table 4?18 shows the status of the cyclone device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual performance of the device under worst-case voltage and juncti on temperature conditions. table 4?18. cyclone device timing model status device preliminary final ep1c3 v ep1c4 v ep1c6 v ep1c12 v ep1c20 v
4?10 altera corporation preliminary january 2007 cyclone device handbook, volume 1 performance the maximum internal logic array cloc k tree frequency is limited to the specifications shown in table 4?19 . table 4?20 shows the cyclone device performance for some common designs. all performance values we re obtained with the quartus ii software compilation of library of parameterized modules (lpm) functions or megafunctions. these performance values are based on ep1c6 devices in 144-pin tqfp packages. table 4?19. clock tree maximum performance specification parameter definition -6 speed grade -7 speed grade -8 speed grade units min typ max min typ max min typ max clock tree f max maximum fre q uency that the clock tree can support for clocking registered logic 405 320 275 mhz table 4?20. cyclone device performance resource used design size & function mode resources used performance les m4k memory bits m4k memory blocks -6 speed grade (mhz) -7 speed grade (mhz) -8 speed grade (mhz) le 16-to-1 multiplexer - 21 - - 405.00 320.00 275.00 32-to-1 multiplexer - 44 - - 317.36 284.98 260.15 16-bit counter - 16 - - 405.00 320.00 275.00 64-bit counter (1) - 66 - - 208.99 181.98 160.75
altera corporation 4?11 january 2007 preliminary timing model internal timing parameters internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?21 through 4?24 describe the cyclone device internal timing microparameters for les, ioes, m4k memory structures, and mu ltitrack interconnects. m4k memory block ram 128 36 bit single port - 4,608 1 256.00 222.67 197.01 ram 128 36 bit simple dual-port mode - 4,608 1 255.95 222.67 196.97 ram 256 18 bit true dual- port mode - 4,608 1 255.95 222.67 196.97 fifo 128 36 bit - 40 4,608 1 256.02 222.67 197.01 shift register 94128 shift register 11 4,536 1 255.95 222.67 196.97 note to table 4?20 : (1) the performance numbers for this function are from an ep1c6 device in a 240-pin pqfp package. table 4?20. cyclone device performance resource used design size & function mode resources used performance les m4k memory bits m4k memory blocks -6 speed grade (mhz) -7 speed grade (mhz) -8 speed grade (mhz) table 4?21. le internal timing microparameter descriptions symbol parameter t su le register setup time before clock t h le register hold time after clock t co le register clock-to-output delay t lut le combinatorial lut delay for data-in to data-out t clr minimum clear pulse width t pre minimum preset pulse width t clkhl minimum clock high or low time
4?12 altera corporation preliminary january 2007 cyclone device handbook, volume 1 table 4?22. ioe internal timing microparameter descriptions symbol parameter t su ioe input and output register setup time before clock t h ioe input and output register hold time after clock t co ioe input and output regist er clock-to-output delay t pin2combout_r row input pin to ioe combinatorial output t pin2combout_c column input pin to ioe combinatorial output t combin2pin_r row ioe data input to combinatorial output pin t combin2pin_c column ioe data input to combinatorial output pin t clr minimum clear pulse width t pre minimum preset pulse width t clkhl minimum clock high or low time table 4?23. m4k block internal timing microparameter descriptions symbol parameter t m4krc synchronous read cycle time t m4kwc synchronous write cycle time t m4kweresu w rite or read enable setup time before clock t m4kwereh w rite or read enable hold time after clock t m4kbesu byte enable setup time before clock t m4kbeh byte enable hold time after clock t m4kdataasu a port data setup time before clock t m4kdataah a port data hold time after clock t m4kaddrasu a port address setup time before clock t m4kaddrah a port address hold time after clock t m4kdatabsu b port data setup time before clock t m4kdatabh b port data hold time after clock t m4kaddrbsu b port address setup time before clock t m4kaddrbh b port address hold time after clock t m4kdataco1 clock-to-output delay when using output registers t m4kdataco2 clock-to-output delay without output registers t m4kclkhl minimum clock high or low time t m4kclr minimum clear pulse width
altera corporation 4?13 january 2007 preliminary timing model figure 4?1 shows the memory waveforms fo r the m4k timing parameters shown in table 4?23 . figure 4?1. dual-port ram timi ng microparameter waveform table 4?24. routing delay internal timing microparameter descriptions symbol parameter t r4 delay for an r4 line with average loading; covers a distance of four lab columns t c4 delay for an c4 line with average loading; covers a distance of four lab rows t local local interconnect delay wrclock wren wraddress data-in reg_data-out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 rdclock a6 din6 unreg_data-out rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 t weresu t wereh t datac o 1 t datac o 2 t datasu t data h t wereh t weresu t waddrsu t waddrh dout0 t rc
4?14 altera corporation preliminary january 2007 cyclone device handbook, volume 1 internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?25 through 4?28 show the internal timing microparameters for les, ioes, trimatrix memory structures, dsp blocks, and multitrack interconnects. table 4?25. le internal timing microparameters symbol -6 -7 -8 unit minmaxminmaxminmax t su 29 33 37 ps t h 12 13 15 ps t co 173 198 224 ps t lut 454 522 590 ps t clr 129 148 167 ps t pre 129 148 167 ps t clkhl 1,234 1,562 1,818 ps table 4?26. ioe internal timing microparameters symbol -6 -7 -8 unit minmaxminmaxminmax t su 348 400 452 ps t h 000ps t co 511 587 664 ps t pin2combout_r 1,130 1,299 1,469 ps t pin2combout_c 1,135 1,305 1,475 ps t combin2pin_r 2,627 3,021 3,415 ps t combin2pin_c 2,615 3,007 3,399 ps t clr 280 322 364 ps t pre 280 322 364 ps t clkhl 1,234 1,562 1,818 ps
altera corporation 4?15 january 2007 preliminary timing model external timing parameters external timing parameters are specified by device density and speed grade. figure 4?2 shows the timing model for bidirectional ioe pin timing. all registers are within the ioe. table 4?27. m4k block internal timing microparameters symbol -6 -7 -8 unit minmaxminmaxminmax t m4krc 4,379 5,035 5,691 ps t m4kwc 2,910 3,346 3,783 ps t m4kweresu 72 82 93 ps t m4kwereh 43 49 55 ps t m4kbesu 72 82 93 ps t m4kbeh 43 49 55 ps t m4kdataasu 72 82 93 ps t m4kdataah 43 49 55 ps t m4kaddrasu 72 82 93 ps t m4kaddrah 43 49 55 ps t m4kdatabsu 72 82 93 ps t m4kdatabh 43 49 55 ps t m4kaddrbsu 72 82 93 ps t m4kaddrbh 43 49 55 ps t m4kdataco1 621 714 807 ps t m4kdataco2 4,351 5,003 5,656 ps t m4kclkhl 1,234 1,562 1,818 ps t m4kclr 286 328 371 ps table 4?28. routing delay internal timing microparameters symbol -6 -7 -8 unit minmaxminmaxminmax t r4 261 300 339 ps t c4 338 388 439 ps t local 244 281 318 ps
4?16 altera corporation preliminary january 2007 cyclone device handbook, volume 1 figure 4?2. external timing in cyclone devices all external i/o timing paramete rs shown are for 3.3-v lvttl i/o standard with the maximum current strength and fast slew rate. for external i/o timing using standards other than lvttl or for different current strengths, use the i/o standard input and output delay adders in tables 4?40 through 4?44 . table 4?29 shows the external i/o timing parameters when using global clock networks. prn clrn dq prn clrn dq prn clrn dq dedicated clock bidirectional pin output register input register oe register t xz t zx t insu t inh t outco table 4?29. cyclone global clock ex ternal i/o timing parameters notes (1) , (2) (part 1 of 2) symbol parameter conditions t i n su setup time for input or bidi rectional pin using ioe input register with global clock fed by clk pin t i n h hold time for input or bidi rectional pin using ioe input register with global clock fed by clk pin t outco clock-to-output delay output or bidirectional pin using ioe output register with global clock fed by clk pin c load = 10 pf t i n supll setup time for input or bidi rectional pin using ioe input register with global clock f ed by enhanced pll with default phase setting t i n hpll hold time for input or bidi rectional pin using ioe input register with global clock fed by enhanced pll with default phase setting
altera corporation 4?17 january 2007 preliminary timing model tables 4?30 through 4?31 show the external timing parameters on column and row pins for ep1c3 devices. t outcopll clock-to-output delay output or bidirectional pin using ioe output register with global clock enhanced pll with default phase setting c load = 10 pf notes to table 4?29 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for ioe pins using a 3.3-v lvttl, 24-ma setting. designers should use the quartus ii software to verify the external timing for any pin. table 4?29. cyclone global clock ex ternal i/o timing parameters notes (1) , (2) (part 2 of 2) symbol parameter conditions table 4?30. ep1c3 column pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 3.085 3.547 4.009 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 4.073 2.000 4.682 2.000 5.295 ns t i n supll 1.795 2.063 2.332 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 2.306 0.500 2.651 0.500 2.998 ns table 4?31. ep1c3 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 3.157 3.630 4.103 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.984 2.000 4.580 2.000 5.180 ns t i n supll 1.867 2.146 2.426 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 2.217 0.500 2.549 0.500 2.883 ns
4?18 altera corporation preliminary january 2007 cyclone device handbook, volume 1 tables 4?32 through 4?33 show the external timing parameters on column and row pins for ep1c4 devices. table 4?32. ep1c4 column pin global clock external i/o timing parameters note (1) symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.471 2.841 3.210 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.937 2.000 4.526 2.000 5.119 ns t i n supll 1.471 1.690 1.910 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 2.080 0.500 2.392 0.500 2.705 ns table 4?33. ep1c4 row pin global clock external i/o timing parameters note (1) symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.600 2.990 3.379 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.991 2.000 4.388 2.000 5.189 ns t i n supll 1.300 1.494 1.689 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 2.234 0.500 2.569 0.500 2.905 ns note to tables 4?32 and 4?33 : (1) contact altera applications fo r ep1c4 device timing parameters.
altera corporation 4?19 january 2007 preliminary timing model tables 4?34 through 4?35 show the external timing parameters on column and row pins for ep1c6 devices. tables 4?36 through 4?37 show the external timing parameters on column and row pins for ep1c12 devices. table 4?34. ep1c6 column pin global cl ock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.691 3.094 3.496 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.917 2.000 4.503 2.000 5.093 ns t i n supll 1.513 1.739 1.964 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 2.038 0.500 2.343 0.500 2.651 ns table 4?35. ep1c6 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.774 3.190 3.605 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.817 2.000 4.388 2.000 4.963 ns t i n supll 1.596 1.835 2.073 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 1.938 0.500 2.228 0.500 2.521 ns table 4?36. ep1c12 column pin global clock external i/o timing parameters (part 1 of 2) symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.510 2.885 3.259 ns t i n h 0.000 0.000 0.000 ns to utco 2.000 3.798 2.000 4.367 2.000 4.940 ns t i n supll 1.588 1.824 2.061 ns
4?20 altera corporation preliminary january 2007 cyclone device handbook, volume 1 tables 4?38 through 4?39 show the external timing parameters on column and row pins for ep1c20 devices. t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 1.663 0.500 1.913 0.500 2.164 ns table 4?37. ep1c12 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.620 3.012 3.404 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.671 2.000 4.221 2.000 4.774 ns t i n supll 1.698 1.951 2.206 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 1.536 0.500 1.767 0.500 1.998 ns table 4?38. ep1c20 column pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.417 2.779 3.140 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.724 2.000 4.282 2.000 4.843 ns t i n supll 1.417 1.629 1.840 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 1.667 0.500 1.917 0.500 2.169 ns table 4?36. ep1c12 column pin global clock external i/o timing parameters (part 2 of 2) symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
altera corporation 4?21 january 2007 preliminary timing model external i/o delay parameters external i/o delay timing parameters for i/o standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. tables 4?40 through 4?45 show the adder delays associated with column and row i/o pins for all packages. if an i/o standard is selected other than lvttl 4 ma with a fast slew rate, add the selected delay to the external t co and t su i/o parameters shown in tables 4?25 through 4?28 . table 4?39. ep1c20 row pin global clock external i/o timing parameters symbol -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t i n su 2.417 2.779 3.140 ns t i n h 0.000 0.000 0.000 ns t outco 2.000 3.724 2.000 4.282 2.000 4.843 ns t xz 3.645 4.191 4.740 ns t zx 3.645 4.191 4.740 ns t i n supll 1.417 1.629 1.840 ns t i n hpll 0.000 0.000 0.000 ns t outcopll 0.500 1.667 0.500 1.917 0.500 2.169 ns t xzpll 1.588 1.826 2.066 ns t zxpll 1.588 1.826 2.066 ns table 4?40. cyclone i/o standard column pin input delay adders (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 000ps 3.3-v lvttl 0 0 0 ps 2.5-v lvttl 27 31 35 ps 1.8-v lvttl 182 209 236 ps 1.5-v lvttl 278 319 361 ps sstl-3 class i ? 250 ? 288 ? 325 ps sstl-3 class ii ? 250 ? 288 ? 325 ps sstl-2 class i ? 278 ? 320 ? 362 ps
4?22 altera corporation preliminary january 2007 cyclone device handbook, volume 1 sstl-2 class ii ? 278 ? 320 ? 362 ps lv d s ? 261 ? 301 ? 340 ps table 4?41. cyclone i/o standard row pin input delay adders i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 000ps 3.3-v lvttl 0 0 0 ps 2.5-v lvttl 27 31 35 ps 1.8-v lvttl 182 209 236 ps 1.5-v lvttl 278 319 361 ps 3.3-v pci (1) 000ps sstl-3 class i ? 250 ? 288 ? 325 ps sstl-3 class ii ? 250 ? 288 ? 325 ps sstl-2 class i ? 278 ? 320 ? 362 ps sstl-2 class ii ? 278 ? 320 ? 362 ps lv d s ? 261 ? 301 ? 340 ps table 4?42. cyclone i/o standard output delay adders for fast slew rate on column pins (part 1 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 0 0 0 ps 4 ma ? 489 ? 563 ? 636 ps 8 ma ? 855 ? 984 ? 1,112 ps 12 ma ? 993 ? 1,142 ? 1,291 ps 3.3-v lvttl 4 ma 0 0 0 ps 8 ma ? 347 ? 400 ? 452 ps 12 ma ? 858 ? 987 ? 1,116 ps 16 ma ? 819 ? 942 ? 1,065 ps 24 ma ? 993 ? 1,142 ? 1,291 ps table 4?40. cyclone i/o standard column pin input delay adders (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
altera corporation 4?23 january 2007 preliminary timing model 2.5-v lvttl 2 ma 329 378 427 ps 8 ma ? 661 ? 761 ? 860 ps 12 ma ? 655 ? 754 ? 852 ps 16 ma ? 795 ? 915 ? 1034 ps 1.8-v lvttl 2 ma 4 4 5 ps 8 ma ? 208 ? 240 ? 271 ps 12 ma ? 208 ? 240 ? 271 ps 1.5-v lvttl 2 ma 2,288 2,631 2,974 ps 4 ma 608 699 790 ps 8 ma 292 335 379 ps sstl-3 class i ? 410 ? 472 ? 533 ps sstl-3 class ii ? 811 ? 933 ? 1,055 ps sstl-2 class i ? 485 ? 558 ? 631 ps sstl-2 class ii ? 758 ? 872 ? 986 ps lv d s ? 998 ? 1, 148 ? 1,298 ps table 4?43. cyclone i/o standard output delay adders for fast slew rate on row pins (part 1 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 0 0 0 ps 4 ma ? 489 ? 563 ? 636 ps 8 ma ? 855 ? 984 ? 1,112 ps 12 ma ? 993 ? 1,142 ? 1,291 ps 3.3-v lvttl 4 ma 0 0 0 ps 8 ma ? 347 ? 400 ? 452 ps 12 ma -858 ? 987 ? 1,116 ps 16 ma ? 819 ? 942 ? 1,065 ps 24 ma ? 993 ? 1,142 ? 1,291 ps 2.5-v lvttl 2 ma 329 378 427 ps 8 ma ? 661 ? 761 ? 860 ps 12 ma ? 655 ? 754 ? 852 ps 16 ma ? 795 ? 915 ? 1,034 ps table 4?42. cyclone i/o standard output delay adders for fast slew rate on column pins (part 2 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
4?24 altera corporation preliminary january 2007 cyclone device handbook, volume 1 1.8-v lvttl 2 ma 1,290 1,483 1,677 ps 8 ma 4 4 5 ps 12 ma ? 208 ? 240 ? 271 ps 1.5-v lvttl 2 ma 2,288 2,631 2,974 ps 4 ma 608 699 790 ps 8 ma 292 335 379 ps 3.3-v pci (1) ? 877 ? 1,009 ? 1,141 ps sstl-3 class i ? 410 ? 472 ? 533 ps sstl-3 class ii ? 811 ? 933 ? 1,055 ps sstl-2 class i ? 485 ? 558 ? 631 ps sstl-2 class ii ? 758 ? 872 ? 986 ps lv d s ? 998 ? 1,148 ? 1,298 ps table 4?44. cyclone i/o standard output delay adders for slow slew rate on column pins (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 1,800 2,070 2,340 ps 4 ma 1,311 1,507 1,704 ps 8 ma 945 1,086 1,228 ps 12 ma 807 928 1,049 ps 3.3-v lvttl 4 ma 1,831 2,105 2,380 ps 8 ma 1,484 1,705 1,928 ps 12 ma 973 1,118 1,264 ps 16 ma 1,012 1,163 1,315 ps 24 ma 838 963 1,089 ps 2.5-v lvttl 2 ma 2,747 3,158 3,570 ps 8 ma 1,757 2,019 2,283 ps 12 ma 1,763 2,026 2,291 ps 16 ma 1,623 1,865 2,109 ps 1.8-v lvttl 2 ma 5,506 6,331 7,157 ps 8 ma 4,220 4,852 5,485 ps 12 ma 4,008 4,608 5,209 ps table 4?43. cyclone i/o standard output delay adders for fast slew rate on row pins (part 2 of 2) standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
altera corporation 4?25 january 2007 preliminary timing model 1.5-v lvttl 2 ma 6,789 7,807 8,825 ps 4 ma 5,109 5,875 6,641 ps 8 ma 4,793 5,511 6,230 ps sstl-3 class i 1,390 1,598 1,807 ps sstl-3 class ii 989 1,137 1,285 ps sstl-2 class i 1,965 2,259 2,554 ps sstl-2 class ii 1,692 1,945 2,199 ps lvds 802 922 1,042 ps table 4?45. cyclone i/o standard output delay adders for slow slew rate on row pins (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max lvcmos 2 ma 1,800 2,070 2,340 ps 4 ma 1,311 1,507 1,704 ps 8 ma 945 1,086 1,228 ps 12 ma 807 928 1,049 ps 3.3-v lvttl 4 ma 1,831 2,105 2,380 ps 8 ma 1,484 1,705 1,928 ps 12 ma 973 1,118 1,264 ps 16 ma 1,012 1,163 1,315 ps 24 ma 838 963 1,089 ps 2.5-v lvttl 2 ma 2,747 3,158 3,570 ps 8 ma 1,757 2,019 2,283 ps 12 ma 1,763 2,026 2,291 ps 16 ma 1,623 1,865 2,109 ps 1.8-v lvttl 2 ma 5,506 6,331 7,157 ps 8 ma 4,220 4,852 5,485 ps 12 ma 4,008 4,608 5,209 ps 1.5-v lvttl 2 ma 6,789 7,807 8,825 ps 4 ma 5,109 5,875 6,641 ps 8 ma 4,793 5,511 6,230 ps 3.3-v pci 923 1,061 1,199 ps table 4?44. cyclone i/o standard output delay adders for slow slew rate on column pins (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max
4?26 altera corporation preliminary january 2007 cyclone device handbook, volume 1 tables 4?46 through 4?47 show the adder delays for the ioe programmable delays. these delays are controlled with the quartus ii software options listed in the parameter column. sstl-3 class i 1,390 1,598 1,807 ps sstl-3 class ii 989 1,137 1,285 ps sstl-2 class i 1,965 2,259 2,554 ps sstl-2 class ii 1,692 1,945 2,199 ps lvds 802 922 1,042 ps note to tables 4?40 through 4?45 : (1) ep1c3 devices do not support the pci i/o standard. table 4?45. cyclone i/o standard output delay adders for slow slew rate on row pins (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit min max min max min max table 4?46. cyclone ioe programmable delays on column pins parameter setting -6 speed grade -7 speed grade -8 speed grade unit min max min max min max decrease input delay to internal cells off 155 178 201 ps small 2,122 2,543 2,875 ps medium 2,639 3,034 3,430 ps large 3,057 3,515 3,974 ps on 155 178 201 ps decrease input delay to input register off 000ps on 3,057 3,515 3,974 ps increase delay to output pin off 000ps on 552 634 717 ps
altera corporation 4?27 january 2007 preliminary timing model maximum input & output clock rates tables 4?48 and 4?49 show the maximum input clock rate for column and row pins in cyclone devices. table 4?47. cyclone ioe programmable delays on row pins parameter setting -6 speed grade -7 speed grade -8 speed grade unit min max min max min max decrease input delay to internal cells off 154 177 200 ps small 2,212 2,543 2,875 ps medium 2,639 3,034 3,430 ps large 3,057 3,515 3,974 ps on 154 177 200 ps decrease input delay to input register off 000ps on 3,057 3,515 3,974 ps increase delay to output pin off 0 0 0 ps on 556 639 722 ps note to table 4?47 : (1) epc1c3 devices do not support the pci i/o standard table 4?48. cyclone maximum input clock rate for column pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 464 428 387 mhz 2.5 v 392 302 207 mhz 1.8 v 387 311 252 mhz 1.5 v 387 320 243 mhz lvcmos 405 374 333 mhz sstl-3 class i 405 356 293 mhz sstl-3 class ii 414 365 302 mhz sstl-2 class i 464 428 396 mhz sstl-2 class ii 473 432 396 mhz lvds 567 549 531 mhz
4?28 altera corporation preliminary january 2007 cyclone device handbook, volume 1 tables 4?50 and 4?51 show the maximum output clock rate for column and row pins in cyclone devices. table 4?49. cyclone maximum input clock rate for row pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 464 428 387 mhz 2.5 v 392 302 207 mhz 1.8 v 387 311 252 mhz 1.5 v 387 320 243 mhz lvcmos 405 374 333 mhz sstl-3 class i 405 356 293 mhz sstl-3 class ii 414 365 302 mhz sstl-2 class i 464 428 396 mhz sstl-2 class ii 473 432 396 mhz 3.3-v pci (1) 464 428 387 mhz lvds 567 549 531 mhz note to tables 4?48 through 4?49 : (1) ep1c3 devices do not support the pci i/ o standard. these parameters are only available on row i/o pins. table 4?50. cyclone maximum output clock rate for column pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 304 304 304 mhz 2.5 v 220 220 220 mhz 1.8 v 213 213 213 mhz 1.5 v 166 166 166 mhz lvcmos 304 304 304 mhz sstl-3 class i 100 100 100 mhz sstl-3 class ii 100 100 100 mhz sstl-2 class i 134 134 134 mhz sstl-2 class ii 134 134 134 mhz lvds 320 320 275 mhz note to table 4?50 : (1) ep1c3 devices do not support the pci i/o standard.
altera corporation 4?29 january 2007 preliminary timing model pll timing table 4?52 describes the cyclone fpga pll specifications. table 4?51. cyclone maximum output clock rate for row pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 296 285 273 mhz 2.5 v 381 366 349 mhz 1.8 v 286 277 267 mhz 1.5 v 219 208 195 mhz lvcmos 367 356 343 mhz sstl-3 class i 169 166 162 mhz sstl-3 class ii 160 151 146 mhz sstl-2 class i 160 151 142 mhz sstl-2 class ii 131 123 115 mhz 3.3-v pci (1) 66 66 66 mhz lvds 320 303 275 mhz note to tables 4?50 through 4?51 : (1) ep1c3 devices do not support the pci i/ o standard. these parameters are only available on row i/o pins. table 4?52. cyclone pll specifications (part 1 of 2) symbol parameter min max unit f i n input fre q uency (-6 speed grade) 15.625 464 mhz input fre q uency (-7 speed grade) 15.625 428 mhz input fre q uency (-8 speed grade) 15.625 387 mhz f i n duty input clock duty cycle 40.00 60 % t i n jitter input clock period jitter 200 ps f out_ext (external pll clock output) pll output fre q uency (-6 speed grade) 15.625 320 mhz pll output fre q uency (-7 speed grade) 15.625 320 mhz pll output fre q uency (-8 speed grade) 15.625 275 mhz
4?30 altera corporation preliminary january 2007 cyclone device handbook, volume 1 f out (to global clock) pll output fre q uency (-6 speed grade) 15.625 405 mhz pll output fre q uency (-7 speed grade) 15.625 320 mhz pll output fre q uency (-8 speed grade) 15.625 275 mhz t out duty duty cycle for external clock output (when set to 50 % ) 45.00 55 % t jitter (1) period jitter for external clock output 300 (2) ps t lock (3) time re q uired to lock from end of device configuration 10.00 100 s f vco pll internal vco operating range 500.00 1,000 mhz - minimum areset time 10 ns n , g0, g1, e counter values 1 32 integer notes to table 4?52 : (1) the t jitter specification for the pll[2..1]_out pins are dependent on the i/o pins in its v ccio bank, how many of them are switching outputs, how much they toggle, and whether or not they use programmable current strength or slow slew rate. (2) f out 100 mhz. when the pll external clock output frequency (f out ) is smaller than 100 mhz, the jitter specification is 60 mui. (3) f in/n must be greater than 200 mhz to ensure correct lock de tect circuit operation below ?20 c. otherwise, the pll operates with the specified parameters under the specified conditions. table 4?52. cyclone pll specifications (part 2 of 2) symbol parameter min max unit
altera corporation 4?31 january 2007 preliminary document revision history document revision history table 4?53 shows the revision history for this document. table 4?53. document revision history date & document version changes made summary of changes january 2007 v1.6 added document revision history. added new row for v cca details in table 4?1 . updated r co n f information in table 4?3 . added new note (12) on voltage overdrive information to table 4?7 and table 4?8 . updated note (9) on r co n f information to ta b l e 4 ? 3 . updated information in ?external i/o delay parameters? section. updated speed grade information in table 4?46 and table 4?47 . updated lvds information in table 4?51 . august 2005 v1.5 minor updates. february 2005 v1.4 updated information on undershoot voltage. updated table 4-2. updated table 4-3. updated the undershoot voltage from 0.5 v to 2.0 v in n ote 3 of table 4-16. updated table 4-17. january 2004 v.1.3 added extended-temperature grade device information. updated table 4-2. updated i cc0 information in table 4-3. october 2003 v.1.2 added clock tree information in table 4-19. finalized timing information for ep1c3 and ep1c12 devices. updated timing information in tables 4-25 through 4-26 and tables 4-30 through 4-51. updated pll specifications in table 4-52. july 2003 v1.1 updated timing information. timing finalized for ep1c6 and ep1c20 devices. updated performance information. added pll timing section. may 2003 v1.0 added document to cyclone device handbook.
4?32 altera corporation preliminary january 2007 cyclone device handbook, volume 1
altera corporation 5?1 january 2007 preliminary 5. reference & ordering information software cyclone ? devices are supported by the altera ? quartus ? ii design software, which provides a comprehe nsive environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced ti ming analysis, signaltap ? ii logic analysis, and device configuration. refer to the design software selector guide for more details on the quartus ii software features. the quartus ii software supports the windows 2000/nt/98, sun solaris, linux red hat v7.1 and hp-ux oper ating systems. it also supports seamless integration with indust ry-leading eda tools through the nativelink ? interface. device pin-outs device pin-outs for cyclone devices ar e available on the altera web site ( www.altera.com ) and in the cyclone fpga device handbook . ordering information figure 5?1 describes the ordering codes for cyclone devices. for more information on a specific package, refer to chapter 15, package information for cyclone devices . figure 5?1. cyclone device pack aging ordering information device type package type 6, 7, or 8 , with 6 being the fastest number of pins for a particular package es: t: q: f: thin quad flat pack (tqfp) plastic quad flat pack (pqfp) fineline bga ep1c: cyclone 3 4 6 12 20 c: i: commercial temperature (t j = 0 ? c to 85 ? c) industrial temperature (t j = -40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count engineering sample 7 ep1c 20 c 400 fes indicates specific device options or shipment method. c51005-1.3
5?2 altera corporation preliminary january 2007 cyclone device handbook, volume 1 document revision history table 5?1 shows the revision history for this document. table 5?1. document revision history date & document version changes made summary of changes january 2007 v1.3 added document revision history. august 2005 v1.2 minor updates. february 2005 v1.1 updated figure 5-1. may 2003 v1.0 added document to cyclone device handbook.

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